DDR2 size with DM648

I'm sorry - to clarify I am using a 900 MHz DM647 processor and my problem occurs after 64 MB, not 16 MB (The loop of 32 bit addressable pointers runs 16M times before throwing an error).

Update:  (Referencing Figure 11 from spruek5a)  With PAGESIZE = 1 and IBANK = 2, Figure 11 says that I should be able to address up to bit #26 or 2^27 = 128MB of DDR.  However, in this configuration, I am only able to address 64MB.  Whenever I try to write to address 0xE400 000 it overwrites what is in address 0xE000 0000.  The EVM has IBANK = 3 because it uses DDR2 chips with 8 banks.  My custom board only has 2 banks, but according to the table I should still be able to achieve the maximum DDR size (shown as 256MB in spruek5a, but known to be 512MB for Rev 1.1 Silicon).  We really don't even need the full 512MB, I just need to be able to get to 256MB and it will be alright.  I don't understand why I'm stuck at 64MB - Is there an issue with the DDR2 Memory Controller when trying to use 2 banks instead of 3?

Thanks in advance.

Jason,

I'm looking into this, but I wonder if you could provide your full DDR2 register configuration? I am not suggesting this is the problem, but as an example this issue could be something as simple as selecting x16 rather than x32 for the bus width. This would effectively limit your addressable memory in half, although in reality you are writing to the full address range. I do not know of any issues with using different values for IBANK, but if I find any I will let you know.

Tim,

Thanks for your reply. Below is the register configuration for DDR2, copied straight from memory.

MIDR:  0x0034031B

DMCSTAT:  0x40000004

SDCFG:  0x00530821

SDRFC:  0x0000081A

SDTIM1:  0x42DB5BD1

SDTIM2:  0x00A4C722

BPRIO:  0x000000FF

DMCCTL:  0x50006405

Our DDR clock (CLKIN2) is not quite the same as the EVM (25 MHz instead of 27 MHz).  I don't think this could produce the effect I am seeing but I thought I'd mention it.

Jason,

Thanks for the register dump. I looked at these (well, really just the SDCFG) and it looks like everything is setup fine register-wise. I do not see any reason you can't access all the memory based on this alone. Have you been able to probe the address lines to ensure they are all toggling correctly? Ideally you would be looking at them on the DDR2 chips themselves to make sure nothing's blocking a row address bit from ever getting to the device.

*edit* If you don't mind, please let me know which memory device you are using so I can take a look at its datasheet.

Are you sure you have a 256 MByte chip as opposed to a 256 Mbit chip?  That would account for 64 MBytes of addressable memory (512 / 8 = 64)

Hi Jason,

I don't know if this will apply to you, but this seems very familiar with what we saw on our DM647.  You say you are using the Lyrtech Gel file as the basis for your DDR2 setup?  We did similiar with both accessing the memory with Code Composer, and also with our Application on startup.  In fact, we also set the DDR2 parameters over the PCI bus before we loaded and booted up via the PCI bus using parameters from the Lyrtech Gel File.

We had the same problem you're describing, which was only 16Mb of our 64Mb memory was accessible with first and last pages repeating themselves in different ranges.  What we found was that the GEL file DDR2 settings had one less row selected for the DDR2 Ram than what we had on our boards.  As soon as we corrected that parameter in the GEL file and also in our application, we were are address the full DDR2 memory range. 

We also found that in PCI Boot Mode, the DDR2 default settings did not have the correct row/columns setting for our DDR2, so we had to change that setting before we loaded the DSP application and let it boot.