UART Tx Empty interrupt not being generated

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BR
Tsvetolin Shulev

That seemed to help/do it, thanks.  

Couple of other things to keep in mind, and that I've learned, for any future reference on this thread:

- the FCR configuration is a bit tricky.  What I've found, as mentioned in the technical reference (SPRUH80C), is that the FIFOEN bit must be set to 1, by itself (no other bits OR'd in), before any other registers in the FCR can be written.  

- the FCR cannot be read at all

- the DMAMODE1 bit must be set to 1, regardless whether DMA is being used or not

For instance, during my FCR configuration, I write twice

FCR = 9

FCR = 0x0F

the first sets the FIFOEN bit, to allow additional writes.  The second hits the FIFOEN bit again, while also setting DMAMODE1 and doing an RXCLR and TXCLR; plus selects 1 byte trigger level for the FIFO ( by writing the 0 to bits 6 and 7 ).

Robert

I have not observed the requirement that DMAMODE1 always be set to 1. For my project, I did not use DMA. I did use FIFOs. My write sequence was
FCR = FIFOEN | RXCLR | TXCLR
FCR = FIFOEN | RXFIFTL
Seemed to work. Changing the FIFO depth changed the flow control timing. Hard to tell directly.

Norman Wong said:

I have not observed the requirement that DMAMODE1 always be set to 1. For my project, I did not use DMA. I did use FIFOs. My write sequence was
FCR = FIFOEN | RXCLR | TXCLR
FCR = FIFOEN | RXFIFTL

Yeah, actually I re-ran without DMAMODE1 enabled, and it was ok too.  Guess I was wrong on that.  I also did the initial FCR write with other bits OR'd in with the FIFOEN, just as you have above, and it was still ok.  Seemed that didn't work previously, but guess it was an oversight.  Means my previous reply can pretty much be disregarded, except about confirming you suggestion that priming the pump is needed to get the first TX interrupt.

Regards,

Robert

Robert56682 said:

- the FCR cannot be read at all

This is a very important point, and a frequent mistake that I see people make, so I wanted to call it out...  The FCR and IIR registers exist at the same address.  Reads from that address are reading IIR.  Writes to that address are writing FCR.  I see people try things like:

// don't do this
FCR |= 1;

That ends up reading IIR, ORing a value of 1, and then writing to FCR.  Needless to say, you can cause a lot of problems that way!

Norman, good tip on "priming the pump".

The need to prime the pump is a less than endearing feature of all 82550/16550 derived UART controllers. Most modern UARTs are level triggered and do not need priming. They are also orthogonal in that all registers are read/write and do not overlap with other registers.

The need to prime the pump outside of the ISR can cause race conditions. Most drivers have to put in critical section in the transmit code to avoid it. Loath to do that.