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c6472 DDR2 PLL discrepency

KatieRoberts-Hoffman
Intellectual 2235 points

Hello,

 

In the 6472 datasheet (http://www.ti.com/lit/gpn/tms320c6472 page 4) I see PLL3 controlling the DDR2 clock, whereas I see PLL2 in the DDR2 Users Guide (focus.ti.com/lit/ug/spru894i/spru894i.pdf page 8).

Can you please confirm the PLL3 from the datasheet is correct?


Thanks,Katie

 

 

 

  • 0
    TI__Mastermind 18136 points

    Hi Katie,

    the datasheet is correct. on the 6474 the PLL2 is controlling the DDR2 clock. The User's guide covers all TCI648x devices so I think the title should be also be C647x I guess. The block diagram you're referring to tries to illustrate a generic view of thoese devises. Not specifically the 6472 - that's where the mismatch comes from.

    Kind regards,

    one and zero