CCS/66AK2H14: CCS/66AK2H14

mahima shanbag

Expert 1585 points

Part Number: 66AK2H14
Other Parts Discussed in Thread: TCI6638K2K, TCI6636K2H, 66AK2H12

Tool/software: Code Composer Studio

We have designed customized board using 66AK2H14. We are using CCSV7 and ti-processor-sdk-rtos-k2hk-evm-04.01.00.06.

we are using TI XDS 110 debug probe .

this is our target configuration.

and we are using C:\ti\ccsv7\ccs_base\emulation\boards\xtcievmk2x\gel gel files .

gel file is loaded successfully with below log

arm_A15_0: GEL Output: Disabling MMU
arm_A15_0: GEL Output: Disabling Caches
arm_A15_0: GEL Output: Invalidate Instruction Caches
arm_A15_0: GEL Output: Enabling non-secure access to cp10 and cp11
arm_A15_0: GEL Output: Enabled non-secure access to cp10 and cp11
arm_A15_0: GEL Output: Enabling SMP bit in ACTLR
arm_A15_0: GEL Output: Enabled SMP bit in ACTLR
arm_A15_0: GEL Output: Entering NonSecure Mode
arm_A15_0: GEL Output: Entered NonSecure Mode
arm_A15_0: GEL Output: Disabling MMU
arm_A15_0: GEL Output: Disabling Caches
arm_A15_0: GEL Output: Invalidate Instruction Caches
arm_A15_0: GEL Output:
Connecting Target...
arm_A15_0: GEL Output: Disabling MMU
arm_A15_0: GEL Output: Disabling Caches
arm_A15_0: GEL Output: Invalidate Instruction Caches
arm_A15_0: GEL Output: Enabling non-secure access to cp10 and cp11
arm_A15_0: GEL Output: Enabled non-secure access to cp10 and cp11
arm_A15_0: GEL Output: Enabling SMP bit in ACTLR
arm_A15_0: GEL Output: Enabled SMP bit in ACTLR
arm_A15_0: GEL Output: Entering NonSecure Mode
arm_A15_0: GEL Output: Entered NonSecure Mode
arm_A15_0: GEL Output: Disabling MMU
arm_A15_0: GEL Output: Disabling Caches
arm_A15_0: GEL Output: Invalidate Instruction Caches
arm_A15_0: GEL Output: TCI6638K2K GEL file Ver is 1.70000005
arm_A15_0: GEL Output: Disabling MMU
arm_A15_0: GEL Output: Disabling Caches
arm_A15_0: GEL Output: Invalidate Instruction Caches
arm_A15_0: GEL Output: Enabling non-secure access to cp10 and cp11
arm_A15_0: GEL Output: Enabled non-secure access to cp10 and cp11
arm_A15_0: GEL Output: Enabling SMP bit in ACTLR
arm_A15_0: GEL Output: Enabled SMP bit in ACTLR
arm_A15_0: GEL Output: Entering NonSecure Mode
arm_A15_0: GEL Output: Entered NonSecure Mode
arm_A15_0: GEL Output: Disabling MMU
arm_A15_0: GEL Output: Disabling Caches
arm_A15_0: GEL Output: Invalidate Instruction Caches
arm_A15_0: GEL Output: Detected PLL bypass enabled: SECCTL[BYPASS] = 0x00800000
arm_A15_0: GEL Output: (2a) MAINPLLCTL1 = 0x00000040
arm_A15_0: GEL Output: (2b) PLLCTL = 0x00000048
arm_A15_0: GEL Output: (2c) PLLCTL = 0x00000048
arm_A15_0: GEL Output: (2d) Delay...
arm_A15_0: GEL Output: (2e) SECCTL = 0x00810000
arm_A15_0: GEL Output: (2f) PLLCTL = 0x0000004A
arm_A15_0: GEL Output: (2g) Delay...
arm_A15_0: GEL Output: (2h) PLLCTL = 0x00000048
arm_A15_0: GEL Output: (4)PLLM[PLLM] = 0x0000000F
arm_A15_0: GEL Output: MAINPLLCTL0 = 0x05000000
arm_A15_0: GEL Output: (5) MAINPLLCTL0 = 0x07000000
arm_A15_0: GEL Output: (5) MAINPLLCTL1 = 0x00000040
arm_A15_0: GEL Output: (6) MAINPLLCTL0 = 0x07000000
arm_A15_0: GEL Output: (7) SECCTL = 0x00890000
arm_A15_0: GEL Output: (8a) Delay...
arm_A15_0: GEL Output: PLL1_DIV3 = 0x00008002
arm_A15_0: GEL Output: PLL1_DIV4 = 0x00008004
arm_A15_0: GEL Output: PLL1_DIV7 = 0x00000000
arm_A15_0: GEL Output: (8d/e) Delay...
arm_A15_0: GEL Output: (10) Delay...
arm_A15_0: GEL Output: (12) Delay...
arm_A15_0: GEL Output: (13) SECCTL = 0x00090000
arm_A15_0: GEL Output: (Delay...
arm_A15_0: GEL Output: (Delay...
arm_A15_0: GEL Output: (14) PLLCTL = 0x00000041
arm_A15_0: GEL Output: PLL has been configured (CLKIN * PLLM / PLLD / PLLOD = PLLOUT):
arm_A15_0: GEL Output: PLL has been configured (122.879997 MHz * 16 / 1 / 2 = 983.039978 MHz)
arm_A15_0: GEL Output: Switching on ARM Core 0
arm_A15_0: GEL Output: Switching on ARM Core 1
arm_A15_0: GEL Output: Switching on ARM Core 2
arm_A15_0: GEL Output: Switching on ARM Core 3
arm_A15_0: GEL Output: ARM PLL has been configured (125.0 MHz * 16 / 2 = 1000.0 MHz)
arm_A15_0: GEL Output: Power on all PSC modules and DSP domains...
arm_A15_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=2, md=9!
arm_A15_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=17, md=25!
arm_A15_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=17, md=26!
arm_A15_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=18, md=27!
arm_A15_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=19, md=28!
arm_A15_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=19, md=29!
arm_A15_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=20, md=30!
arm_A15_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=20, md=31!
arm_A15_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=20, md=32!
arm_A15_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=20, md=33!
arm_A15_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=21, md=34!
arm_A15_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=22, md=35!
arm_A15_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=22, md=36!
arm_A15_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=23, md=37!
arm_A15_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=23, md=38!
arm_A15_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=24, md=39!
arm_A15_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=24, md=40!
arm_A15_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=24, md=41!
arm_A15_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=24, md=42!
arm_A15_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=25, md=43!
arm_A15_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=25, md=44!
arm_A15_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=25, md=45!
arm_A15_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=25, md=46!
arm_A15_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=26, md=47!
arm_A15_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=27, md=48!
arm_A15_0: GEL Output: Power on all PSC modules and DSP domains... Done.
arm_A15_0: GEL Output: WARNING: SYSCLK is the input to the PA PLL.
arm_A15_0: GEL Output: Completed PA PLL Setup
arm_A15_0: GEL Output: PAPLLCTL0 - before: 0x0x098804C0 after: 0x0x09080500
arm_A15_0: GEL Output: PAPLLCTL1 - before: 0x0x00000040 after: 0x0x00002040
arm_A15_0: GEL Output: DDR begin
arm_A15_0: GEL Output: XMC setup complete.
arm_A15_0: GEL Output: DDR3 PLL (PLL2) Setup ...
arm_A15_0: GEL Output: DDR3 PLL Setup complete, DDR3A clock now running at 666 MHz.
arm_A15_0: GEL Output: DDR3A initialization complete
arm_A15_0: GEL Output: DDR done
arm_A15_0: GEL Output: Entering A15 non secure mode ..
arm_A15_0: GEL Output: Disabling MMU
arm_A15_0: GEL Output: Disabling Caches
arm_A15_0: GEL Output: Invalidate Instruction Caches
arm_A15_0: GEL Output: Enabling non-secure access to cp10 and cp11
arm_A15_0: GEL Output: Enabled non-secure access to cp10 and cp11
arm_A15_0: GEL Output: Enabling SMP bit in ACTLR
arm_A15_0: GEL Output: Enabled SMP bit in ACTLR
arm_A15_0: GEL Output: Entering NonSecure Mode
arm_A15_0: GEL Output: Entered NonSecure Mode
arm_A15_0: GEL Output: Disabling MMU
arm_A15_0: GEL Output: Disabling Caches
arm_A15_0: GEL Output: Invalidate Instruction Caches
arm_A15_0: GEL Output: A15 non secure mode entered

but when we try to load the program to arm core0 it is giving following error.

arm_A15_0: Trouble Reading Memory Block at 0x80000000 on Page 0 of Length 0x4: (Error -1205 @ 0x80000000) Device memory bus has an error and may be hung. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 6.0.628.3)
arm_A15_0: File Loader: Verification failed: Target failed to read 0x80000000
arm_A15_0: GEL: File: C:\Users\admin\workspace_v7\I2C_BasicExample_K2H_armTestProject\Debug\I2C_BasicExample_K2H_armTestProject.out: Load failed.
arm_A15_0: Unable to terminate memory download: NULL buffer pointer at 0x3aa4
arm_A15_0: Trouble Reading Register REG_SYSTEM_TARGET_CONFIG: (Error -1141 @ 0x3D58) Device is not responding to the request. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 6.0.628.3)
arm_A15_0: Trouble Reading Register REG_SYSTEM_MMU_CONFIG: (Error -1141 @ 0x3D58) Device is not responding to the request. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 6.0.628.3)

we are using 4GB DDR3 64 bit.

when we try to read/write from DDR3 using GEL ddr3A_memory_test() it is giving below errors.

arm_A15_0: Trouble Writing Memory Block at 0x80000000 on Page 0 of Length 0x4: (Error -1141 @ 0x3D58) Device is not responding to the request. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 6.0.628.3)
arm_A15_0: GEL: Error while executing OnTargetConnect(): Target failed to write 0x80000000
   at *(index)=index [xtcievmk2x_arm.gel:1499]
   at ddr3A_memory_test() [xtcievmk2x_arm.gel:689]
   at Global_Default_Setup_Silent() [xtcievmk2x_arm.gel:597]
   at OnTargetConnect()
arm_A15_0: Trouble Reading Register REG_SYSTEM_TARGET_CONFIG: (Error -1141 @ 0x3D58) Device is not responding to the request. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 6.0.628.3)
arm_A15_0: Trouble Reading Register REG_SYSTEM_MMU_CONFIG: (Error -1141 @ 0x3D58) Device is not responding to the request. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 6.0.628.3)
arm_A15_0: Trouble Reading Register REG_SYSTEM_MMU_STATUS: (Error -1141 @ 0x3D58) Device is not responding to the request. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 6.0.628.3)
arm_A15_0: Trouble Reading Register REG_SYSTEM_MMU_STATUS: (Error -1141 @ 0x3D58) Device is not responding to the request. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 6.0.628.3)

Q1. Do we need to change anything in the GEL file?

Q2. Whether we have to change this 0x80000000 to some other value.

Please help me to solve these errors.

Thank you,

Mahima Shanbag

over 7 years ago

0 Cvetolin Shulev-XID over 7 years ago

TI__Guru 65405 points

The team is notified. They will post their feedback directly here.

BR
Tsvetolin Shulev

0 Yordan Kovachev over 7 years ago in reply to Cvetolin Shulev-XID

TI__Guru**** 161600 points

Hi,

When you create the target configuration file, can you try selecting the 66AK2H12 device instead of TCI6636K2H?

Best Regards,
Yordan

0 mahima shanbag over 7 years ago in reply to Yordan Kovachev

Expert 1585 points

Hi Yordan,
I tried with 66AK2H12 but It gave me same error.
Even I tried different DDR3 frequency.

0 Rahul Prabhu over 7 years ago in reply to mahima shanbag

TI__Guru** 116170 points

Mahima,

You are probably using different DDR3 part on your custom board that needs modifications of EMIF controller timing registers, and changes to HW PHY and leveling. This is one of the required steps when migrating from TI evaluation platform to custom hardware. TI provides the Keystone 2 DDR3 Register Calculation Spreadsheet to help populate the DDR3 EMIF registers and to help with the PHY configuration. Link is in section 2.1.1 in the app note link that I have provided below.

I would recommend that you refer to the DDR3 Debug App notes :
www.ti.com/.../sprac04.pdf

After you run the GEL file, before loading a application into DDR, it is always a good sanity check if you can open a memory browser window and try and write to 10-12 words in the base of DDR memory or run a memory read/write test using a GEL script.

Hope this helps.

Regards,
Rahul

0 Rahul Prabhu over 7 years ago in reply to Rahul Prabhu

TI__Guru** 116170 points

Mahima,

From a software perspective, after the GEL file chnages to DDR are verified, you will also need to update the values in the board library if you are using RTOS and uboot if you are using Linux before porting your application and system boot to your custom board.

Regards,
Rahul

0 mahima shanbag over 7 years ago in reply to Rahul Prabhu

Expert 1585 points

Hi Rahul,

Sorry for the late reply.

Actually I was doing memory read/write test using a GEL script.

It was giving below error for both Arm and DSP core:

Trouble Writing Memory Block at 0x80000000 on Page 0 of Length 0x4: (Error -1141 @ 0x3D58) Device is not responding to the request. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 6.0.628.3).

I referred this link

I changed DDR3A_PGCR2 = 0x00F07A12 to DDR3A_PGCR2 = 0x00F87A12 in ddr3A_64bit_DDR1600_setup()

Then I was getting below log for ARM and DSP cores.

For ARM core :

arm_A15_0: GEL Output: Disabling MMU

arm_A15_0: GEL Output: Disabling Caches

arm_A15_0: GEL Output: Invalidate Instruction Caches

arm_A15_0: GEL Output: Enabling non-secure access to cp10 and cp11

arm_A15_0: GEL Output: Enabled non-secure access to cp10 and cp11

arm_A15_0: GEL Output: Enabling SMP bit in ACTLR

arm_A15_0: GEL Output: Enabled SMP bit in ACTLR

arm_A15_0: GEL Output: Entering NonSecure Mode

arm_A15_0: GEL Output: Entered NonSecure Mode

arm_A15_0: GEL Output: Disabling MMU

arm_A15_0: GEL Output: Disabling Caches

arm_A15_0: GEL Output: Invalidate Instruction Caches

arm_A15_0: GEL Output:

Connecting Target...

arm_A15_0: GEL Output: Disabling MMU

arm_A15_0: GEL Output: Disabling Caches

arm_A15_0: GEL Output: Invalidate Instruction Caches

arm_A15_0: GEL Output: Enabling non-secure access to cp10 and cp11

arm_A15_0: GEL Output: Enabled non-secure access to cp10 and cp11

arm_A15_0: GEL Output: Enabling SMP bit in ACTLR

arm_A15_0: GEL Output: Enabled SMP bit in ACTLR

arm_A15_0: GEL Output: Entering NonSecure Mode

arm_A15_0: GEL Output: Entered NonSecure Mode

arm_A15_0: GEL Output: Disabling MMU

arm_A15_0: GEL Output: Disabling Caches

arm_A15_0: GEL Output: Invalidate Instruction Caches

arm_A15_0: GEL Output: TCI6638K2K GEL file Ver is 1.89999998

arm_A15_0: GEL Output: Disabling MMU

arm_A15_0: GEL Output: Disabling Caches

arm_A15_0: GEL Output: Invalidate Instruction Caches

arm_A15_0: GEL Output: Enabling non-secure access to cp10 and cp11

arm_A15_0: GEL Output: Enabled non-secure access to cp10 and cp11

arm_A15_0: GEL Output: Enabling SMP bit in ACTLR

arm_A15_0: GEL Output: Enabled SMP bit in ACTLR

arm_A15_0: GEL Output: Entering NonSecure Mode

arm_A15_0: GEL Output: Entered NonSecure Mode

arm_A15_0: GEL Output: Disabling MMU

arm_A15_0: GEL Output: Disabling Caches

arm_A15_0: GEL Output: Invalidate Instruction Caches

arm_A15_0: GEL Output: Detected PLL bypass enabled: SECCTL[BYPASS] = 0x00800000

arm_A15_0: GEL Output: (2a) MAINPLLCTL1 = 0x00000040

arm_A15_0: GEL Output: (2b) PLLCTL = 0x00000048

arm_A15_0: GEL Output: (2c) PLLCTL = 0x00000048

arm_A15_0: GEL Output: (2d) Delay...

arm_A15_0: GEL Output: (2e) SECCTL = 0x00810000

arm_A15_0: GEL Output: (2f) PLLCTL = 0x0000004A

arm_A15_0: GEL Output: (2g) Delay...

arm_A15_0: GEL Output: (2h) PLLCTL = 0x00000048

arm_A15_0: GEL Output: (4)PLLM[PLLM] = 0x0000000F

arm_A15_0: GEL Output: MAINPLLCTL0 = 0x05000000

arm_A15_0: GEL Output: (5) MAINPLLCTL0 = 0x07000000

arm_A15_0: GEL Output: (5) MAINPLLCTL1 = 0x00000040

arm_A15_0: GEL Output: (6) MAINPLLCTL0 = 0x07000000

arm_A15_0: GEL Output: (7) SECCTL = 0x00890000

arm_A15_0: GEL Output: (8a) Delay...

arm_A15_0: GEL Output: PLL1_DIV3 = 0x00008002

arm_A15_0: GEL Output: PLL1_DIV4 = 0x00008004

arm_A15_0: GEL Output: PLL1_DIV7 = 0x00000000

arm_A15_0: GEL Output: (8d/e) Delay...

arm_A15_0: GEL Output: (10) Delay...

arm_A15_0: GEL Output: (12) Delay...

arm_A15_0: GEL Output: (13) SECCTL = 0x00090000

arm_A15_0: GEL Output: (Delay...

arm_A15_0: GEL Output: (14) PLLCTL = 0x00000041

arm_A15_0: GEL Output: PLL has been configured (CLKIN * PLLM / PLLD / PLLOD = PLLOUT):

arm_A15_0: GEL Output: PLL has been configured (122.879997 MHz * 16 / 1 / 2 = 983.039978 MHz)

arm_A15_0: GEL Output: Switching on ARM Core 0

arm_A15_0: GEL Output: Switching on ARM Core 1

arm_A15_0: GEL Output: Switching on ARM Core 2

arm_A15_0: GEL Output: Switching on ARM Core 3

arm_A15_0: GEL Output: ARM PLL has been configured (125.0 MHz * 16 / 2 = 1000.0 MHz)

arm_A15_0: GEL Output: DISABLESTAT ---> 0x000007FF

arm_A15_0: GEL Output: Power on all PSC modules and DSP domains...

arm_A15_0: GEL Output: Power on all PSC modules and DSP domains... Done.

arm_A15_0: GEL Output: WARNING: SYSCLK is the input to the PA PLL.

arm_A15_0: GEL Output: Completed PA PLL Setup

arm_A15_0: GEL Output: PAPLLCTL0 - before: 0x0x098804C0 after: 0x0x09080500

arm_A15_0: GEL Output: PAPLLCTL1 - before: 0x0x00000040 after: 0x0x00002040

arm_A15_0: GEL Output: DDR begin

arm_A15_0: GEL Output: XMC setup complete.

arm_A15_0: GEL Output: DDR3 PLL Setup ...

arm_A15_0: GEL Output: DDR3 PLL Setup complete, DDR3A clock now running at 800 MHz.

arm_A15_0: GEL Output: DDR3A initialization complete

arm_A15_0: GEL Output: DDR done

arm_A15_0: GEL Output: DDR3A memory test... Started

arm_A15_0: GEL: Error while executing OnTargetConnect(): Target failed to write 0x80000000

at *(index)=index [xtcievmk2x_arm_EMENI.gel:1499]

at ddr3A_memory_test() [xtcievmk2x_arm_EMENI.gel:689]

at Global_Default_Setup_Silent() [xtcievmk2x_arm_EMENI.gel:597]

at OnTargetConnect()

arm_A15_0: Trouble Reading Register REG_SYSTEM_TARGET_CONFIG: (Error -1141 @ 0x3D58) Device is not responding to the request. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 6.0.628.3)

For DSP core:

C66xx_0: GEL Output:
Connecting Target...
C66xx_0: GEL Output: TCI6638K2K GEL file Ver is 1.70000005
C66xx_0: GEL Output: Detected PLL bypass disabled: SECCTL[BYPASS] = 0x00000000
C66xx_0: GEL Output: (3a) PLLCTL = 0x00000040
C66xx_0: GEL Output: (3b) PLLCTL = 0x00000040
C66xx_0: GEL Output: (3c) Delay...
C66xx_0: GEL Output: (4)PLLM[PLLM] = 0x0000000F
C66xx_0: GEL Output: MAINPLLCTL0 = 0x07000000
C66xx_0: GEL Output: (5) MAINPLLCTL0 = 0x07000000
C66xx_0: GEL Output: (5) MAINPLLCTL1 = 0x00000040
C66xx_0: GEL Output: (6) MAINPLLCTL0 = 0x07000000
C66xx_0: GEL Output: (7) SECCTL = 0x00090000
C66xx_0: GEL Output: (8a) Delay...
C66xx_0: GEL Output: PLL1_DIV3 = 0x00008002
C66xx_0: GEL Output: PLL1_DIV4 = 0x00008004
C66xx_0: GEL Output: PLL1_DIV7 = 0x00000000
C66xx_0: GEL Output: (8d/e) Delay...
C66xx_0: GEL Output: (10) Delay...
C66xx_0: GEL Output: (12) Delay...
C66xx_0: GEL Output: (13) SECCTL = 0x00090000
C66xx_0: GEL Output: (Delay...
C66xx_0: GEL Output: (Delay...
C66xx_0: GEL Output: (14) PLLCTL = 0x00000041
C66xx_0: GEL Output: PLL has been configured (CLKIN * PLLM / PLLD / PLLOD = PLLOUT):
C66xx_0: GEL Output: PLL has been configured (122.879997 MHz * 16 / 1 / 2 = 983.039978 MHz)
C66xx_0: GEL Output: DISABLESTAT ---> 0x000007FF
C66xx_0: GEL Output: Power on all PSC modules and DSP domains...
C66xx_0: GEL Output: Power on all PSC modules and DSP domains... Done.
C66xx_0: GEL Output: WARNING: SYSCLK is the input to the PA PLL.
C66xx_0: GEL Output: Completed PA PLL Setup
C66xx_0: GEL Output: PAPLLCTL0 - before: 0x0x09080500 after: 0x0x09080500
C66xx_0: GEL Output: PAPLLCTL1 - before: 0x0x00002040 after: 0x0x00002040
C66xx_0: GEL Output: DDR begin
C66xx_0: GEL Output: XMC setup complete.
C66xx_0: GEL Output: DDR3 PLL Setup ...
C66xx_0: GEL Output: DDR3 PLL Setup complete, DDR3A clock now running at 800 MHz.
C66xx_0: GEL Output: DDR3A initialization complete
C66xx_0: GEL Output: DDR3A memory test... Started
C66xx_0: GEL Output: DDR3A memory test... Passed
C66xx_0: GEL Output: DDR done

Q1. how to solve Trouble Writing Memory Block at 0x80000000 on Page 0 of Length 0x4 for ARM core.

Q2. We are using same DDR3 for ARM and DSP then why it is giving error for ARM , Timing values are same for both the cores in GEL file.

Q3. Is there any other configuration for ARM core?

Please help me with this.

Thank you,

Mahima Shanbag

0 mahima shanbag over 7 years ago in reply to mahima shanbag

Expert 1585 points

Hi Rahul,

I am Trying to run one application which glows the LED in our board.

I attached my application here

Fullscreen 1854.hello.c Download

/*
 *  ======== hello.c ========
 *  The hello example serves as a basic sanity check program for SYS/BIOS. It
 *  demonstrates how to print the string "hello world" to stdout. 
 */




/*
 * Copyright (c) 2014 iWave Systems Technologies Pvt. Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 3
 * as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; If not, see <http://www.gnu.org/licenses/>.
 */

/*
 * @file gpio_led_emeni.c
 *
 *
 *
 *
 */

#include <stdio.h>
#include <stdlib.h>
#include <hw_types.h>
//#include <ti/drv/gpio/test/led_blink/src/printf.h>
#include <ti/board/board.h>
#include <xdc/std.h>

#include <xdc/runtime/System.h>
#include <ti/sysbios/BIOS.h>
#define GPIO29 29
#define GPIO28 28
#define GPIO30 30
#define GPIO31 31


#define DIR_REG 0x00000010
#define OUT_DATA 0x00000014
#define SET_DATA 0x00000018
#define CLR_DATA 0x0000001C
#define IN_DATA 0x00000020
#define  BASE_ADDR  0X0260BF00 /* GPIO config start address*/

#define ERROR_VAL -1
#define mask1 0xEFFFFFFF /*gpio28 for setting output*/
#define mask2 0xDFFFFFFF /*gpio29 for setting output */
#define mask3 0xBFFFFFFF /*gpio30 for setting output */
#define mask4 0x7FFFFFFF /*gpio29 for setting output */

#define mask5 0x10000000 /*gpio28 for set_data and clr_data */
#define mask6 0x20000000 /*gpio29 for set_data and clr_data */
#define mask7 0x40000000 /*gpio29 for set_data and clr_data */
#define mask8 0x80000000 /*gpio29 for set_data and clr_data */

 /*******************************************************************************
  * Function:    gpio_direction_output
  *
  * Description: This function is used to set particular GPIO pin as output
  *
  * Parameters:  gpio-gpio pin to be setted as direction output
  *
  * Return Value: masked written value
  *
  *****************************************************************************/

void gpio_direction_output(unsigned gpio)
{
        uint32_t readval;
        uint32_t val1;
        readval=HW_RD_REG32(BASE_ADDR+DIR_REG);
        if(gpio==GPIO28) /* CP's user led1*/
                val1= readval & mask1;
        else if(gpio==GPIO29) /*CP's user led2 and DP's user led1*/
                val1= readval & mask2;
        else if(gpio==GPIO30) /* CP's user led3 and DP's user led2*/
                val1= readval & mask3;
        else if(gpio==GPIO31) /*DP's user led3*/
                val1= readval & mask4;
         HW_WR_REG32(BASE_ADDR+DIR_REG,val1);

}
/*******************************************************************************
  * Function:    gpio_set_state
  *
  * Description: This function is used to set particular GPIO pin as 0/1
  *
  * Parameters:  gpio-gpio pin to be set
  *
  * Return Value: masked written value
  *
  *****************************************************************************/

void gpio_set_state(unsigned gpio,int state)
{
        uint32_t readval;
        uint32_t val1;
        if(gpio==GPIO28)
        {
                if(state==1)/*set CP's user led1 to high*/
                {
                        readval=HW_RD_REG32(BASE_ADDR+SET_DATA);
                        val1=readval | mask5;
                        HW_WR_REG32(BASE_ADDR+SET_DATA,val1);
        }
                else if (state==0) /*set CP's user led1 to low*/
                {
                        readval=HW_RD_REG32(BASE_ADDR+CLR_DATA);
                        val1=readval | mask5;
                        HW_WR_REG32(BASE_ADDR+CLR_DATA,val1);
                }
        }
        else if(gpio==GPIO29)
        {
                if(state==1)  /*set CP's user led2 and DP's user led1 to high*/
                {
                        readval=HW_RD_REG32(BASE_ADDR+SET_DATA);
                        val1=readval | mask6;
                        HW_WR_REG32(BASE_ADDR+SET_DATA,val1);
                }
                else if (state==0)  /*set CP's user led2 and DP's user led1 to low*/
                {
                        readval=HW_RD_REG32(BASE_ADDR+CLR_DATA);
                        val1=readval | mask6;
                        HW_WR_REG32(BASE_ADDR+CLR_DATA,val1);
                }
        }
        else if(gpio==GPIO30)
        {
                if(state==1)   /*set CP's user led3 and DP's user led2 to high*/
                {
                        readval=HW_RD_REG32(BASE_ADDR+SET_DATA);
                        val1=readval | mask7;
                        HW_WR_REG32(BASE_ADDR+SET_DATA,val1);
                }
                else if (state==0)   /*set CP's user led3 and DP's user led2 to low*/
                {
                        readval=HW_RD_REG32(BASE_ADDR+CLR_DATA);
                        val1=readval | mask7;
                        HW_WR_REG32(BASE_ADDR+CLR_DATA,val1);
                }
        }
        else if(gpio==GPIO31)
        {
                if(state==1)  /*set DP's user led3 to high*/
                {
                        readval=HW_RD_REG32(BASE_ADDR+SET_DATA);
                        val1=readval | mask8;
                        HW_WR_REG32(BASE_ADDR+SET_DATA,val1);
                }
        else if (state==0)  /*set DP's user led3 to low*/
                {
                        readval=HW_RD_REG32(BASE_ADDR+CLR_DATA);
                        val1=readval | mask7;
                        HW_WR_REG32(BASE_ADDR+CLR_DATA,val1);
                }

    }

}

/*******************************************************************************
  * Function:    led_init
  *
  * Description: This function is used to initialize GPIO
  *
  * Parameters:  none
  *
  * Return Value: -1--on error
            any integer value-- on success
  *
  *****************************************************************************/
void led_init(void)
{
     /*Set direction of GPIO as output*/
    gpio_direction_output(GPIO28); /*SET CP's user led1 as direction output*/
    gpio_direction_output(GPIO29);/*set CP's user led2 and DP's user led1 as direction output*/
    gpio_direction_output(GPIO30);/*set CP's user led3 and DP's user led2 as direction output*/
    gpio_direction_output(GPIO31);/*set DP's user led3 as direction output*/
}
/******************************************************************
 Function: main
*
******************************************************************/
int main(void)
{

    Board_initCfg boardCfg;

        int choice;
        int lednum;

        boardCfg = BOARD_INIT_MODULE_CLOCK |
                 BOARD_INIT_PINMUX_CONFIG |
                 BOARD_INIT_DDR |
                 BOARD_INIT_PLL |
                 BOARD_INIT_UART_STDIO;
        boardCfg &= 0xFFFFFFDF;
        if (Board_init(boardCfg))
            {
                return -1;
            }

        do{
        printf("Enter the choice:\n");
        printf("1: LED ON\n");
        printf("2: LED OFF\n");
        printf("Enter 0 to quit\n");
        scanf("%d",&choice);
        printf("Enter the LED number to glow according to below given conditions:\n");
        printf("For CP:28,29,30 and DP1 and DP2: 29,30,31\n");
        scanf("%d",&lednum);
        switch(choice)
        {
                case 1:
                         led_init();/* GPIO initialization */
                        /* Write high to gpio pin to control LED's */
                        if(lednum==28)  /* CP's user led1*/
                         {
                               gpio_set_state(GPIO28,1);
                         }
                        else if(lednum==29)  /*CP's user led2 and DP's user led1*/
                         {
                                gpio_set_state(GPIO29,1);
                         }
                        else if(lednum==30) /* CP's user led3 and DP's user led2*/
                       {
                                gpio_set_state(GPIO30,1);
                       }
                        else if(lednum==31)/*DP's user led3*/
                       {
                                gpio_set_state(GPIO31,1);
                       }
                        printf("\n GPIO Led ON \n");
                        break;
                case 2:/* GPIO initialization */
                         led_init();
                        /* Write low to gpio pin to control LED1 */
                         if(lednum==28)  /* CP's user led1*/
                         {
                                gpio_set_state(GPIO28,0);
                         }
                        else if(lednum==29)   /*CP's user led2 and DP's user led1*/
                        {
                             gpio_set_state(GPIO29,0);
                         }
                        else if(lednum==30) /*CP's user led2 and DP's user led1*/
                        {
                                gpio_set_state(GPIO30,0);
                        }
                        else if(lednum==31)  /*DP's user led3*/
                        {
                                gpio_set_state(GPIO31,0);
                        }
                       /*printf("\n GPIO Led OFF \n");*/
                        printf("GPIO LED OFF\n");
                        break;
                default:
                        printf("\n Wrong option \n");
                        printf("Enter the below options:\n");
                        printf("A: LED ON\n");
                        printf("B: LED OFF\n");
                        printf("Enter 0 to quit\n");

        }
      }while(choice!=0);
        BIOS_exit(0);  /* terminates program and dumps SysMin output */
        return 0;
}

I am using board_init() in my application, which is successfully initializing the DDR and PLL's.

I built this application to DSP.

When I try to use flash_writer in my board It is getting aborted in SBL_socInit().

I checked in SBL_socInit() , it was returning -1 .

int32_t SBL_socInit()
{
    Board_initCfg boardCfg;
    boardCfg = BOARD_INIT_PLL |
        BOARD_INIT_MODULE_CLOCK |
        BOARD_INIT_DDR |
        BOARD_INIT_UART_STDIO;

#if defined(A15_CORE)
    void (*monitorFunction) (void (*)(void), ...);

    /* A15 startup calls */
    monitorFunction = (void (*)) 0x1000;
    (*monitorFunction)(SBL_setNSMode);
    (*monitorFunction)(SBL_a15EnableNeon);
    (*monitorFunction)(SBL_a15EnableSMP);
#endif

    /* Board Library Init. */
    if (Board_init(boardCfg))
    {
        return -1;
    }
    return 0;
}

This is due to Board_init() .

Board_init() is returning -7 that means BOARD_INIT_DDR_FAIL.

Now my question is:

Q1. Function Board_init() which is successfully initializing the DDR in my application is giving error in Flash_writer.What may be the issue?

Its really confusing.Please help me with this.

Thank you,

Mahima Shanbag

0 Rahul Prabhu over 7 years ago in reply to mahima shanbag

TI__Guru** 116170 points

Mahima,

I believe that you are running into the same issue as was reported here:
e2e.ti.com/.../2423288

Can you please add the following line of code after the monitor functions have been called:
SBL_a15EnableVFP11co();

Another debug step would be, if you are running the flash writer from CCS, the GEL does the DDR init so you can comment out that option in your boardCfg and skip that step all together and see if the flash writer proceeds.

Can you confirm that when the DDR is initialized from your application, are you able to open the Memory browser and do a read and Write? Also, are you using GEL file also to initialize DDR or is the application the only software configuring the DDR. If DDR is initialized from application can you confirm that the application is running from MSMC ?

Regards,
Rahul

0 mahima shanbag over 7 years ago in reply to Rahul Prabhu

Expert 1585 points

Hi Rahul,

I just commented SBL_socInit() as I am using GEL file to configure the DDR.

but flash_writer get aborted with below prints.

Opening SPI handle...

SPI init failed!

In our custom board we are using MT25QU512ABB NOR FLASH.

Is there any other configuration I have to change?

I have changed the deviceID in board_flash.h as below

BOARD_FLASH_ID_NORN25Q128 = 0xBB20.

Regards,

Mahima Shanbag

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