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Problem in enabling MMU and cache in DM6446

satish2268
Prodigy 40 points

Hi All, I had ported my code on ARM sub-system of DM6446.Its running fine.But, when i enable MMU and D/I Cache through advanced options provided in ARM IDE,then code crashes.

Can anyone tell me why it crashes? [:(]

In davincievm_arm.gel(provided by TI),once MMU is disabled and cache flush is done then why ARM caches are not enabled again? Is code running on ARM sub-system with cache disabled?

Thanks In Advance,

satish

  • 0
    TI__Mastermind 37340 points

    Satish,

    Since you mentioned GEL file and IDE, is it safe to assume that you are using CCS as your IDE?  If so, please note that CCS is not Linux aware and therefore does not know how to handle MMU.  You can use it to program and debug ARM9 applications at a very low level, but anything requiring an OS on the ARM (or enabling MMU) will likely not work.

  • 0 in reply to Juan Gonzales
    Prodigy 40 points

    Thanks for the quick reply............

    If CCS is not aware of how to handle MMU,then why options were given in CCS to enable MMU,Inst/Data cache?

    Is the code running with ARM internal cache disabled?If so then where can i insert my ARM asm code to enable MMU,Inst/Data cache?

    Simulator Issue:

                   When i had enabled profiling in TMS470R Simulator,its allowing to select only CPU cycles option, but not Total cycles. So,is there anyway to see Cache Miss/Hits in this simulator?

     

    Thanks In Advance,

    satish

  • 0 in reply to satish2268
    TI__Intellectual 755 points

    Satish,

    This is with respect to your simulator issue.

    When you say "TMS470R" Simulator, did you select ARM9e Simulator? If the simulator is only a CPU or core simulator, it only provides CPU cycles, as it just models the core + flat memory (no latency).

    You will not be able to get Cache miss/hits for a CPU simulator as it does not simulate caches.

    On the other hand, if you chose the ARM926 Simulator, you will get CPU and Total cycles as this simulator simulates the core, cahes, MMU,write bufferes and external memory. But this configuration does not provide cache hits/misses counts.

    Regards,

    Anuradha.

     

     

     

     

  • 0 in reply to Anuradha Krishnan
    Prodigy 40 points

    Hi Anuradha,

       Thank you for the reply to the 3rd question............. [:)]

    Can anyone throw some light on my 1st & 2nd questions?[:(]

     

    Thanks In Advance,

    satish

     

  • 0 in reply to satish2268
    TI__Mastermind 37340 points

    Unfortunately, I am not familiar enough with CCS.  I can confirm that CCS 3.x is not Linux aware, primarily due to its inability to hadle ARM MMU.  I was not aware there was an option to enable MMU, as I do not use CCS much, so perhaps someone more familiar with CCS can chime in.

    With ragards to enabling cache and so forth, I believe this is all managemed by MMU kernel software in Linux.  Becuase of this, I do not think GEL file enables these features. 

    That said, my I ask what you will be ultimately running on ARM?  ARM is a complex CPU and its use is normally encapsulated by a high level OS (WinCE, Linux, ....).  Do you not plan to have any OS in the ARM?  If so, you will likely have to write a good amount of code to take care of MMU and other features as you are finding out (your own customized OS, or subset of OS).   All the source code (including MMU code) for the Linux Kernel is included in our DVSDK, so you can definitely use this as reference code for you purposes; however, as you will probrably be able to confirm, this is a lot of code to port.