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TMS320DM8168: Sending YCbCr data on the Video Input VIN0 bus

Part Number: TMS320DM8168

I need to send interlaced YCbCr data to the TI using the VIN0 bus. I cannot find a timing diagram which shows how hsync, vsync and data enable are used. And where in the SDK can you set the use of data enable because i have a working design for RGB where the data enable is tied low i.e. not used.

Also, can this TI chip handle 60 frames per second to do deinterlacing along with 4;2:2 to 4:4:4 and conversion to RGB at the full frame rate of 60fps.

  • Hello,

    What is the software release that you are using here?

    BR
    Margarita
  • Hello,

    You could check TRM chapter "2.11 Video Input Parser (VIP) Module".
    I would recommend you to check this link also:
    e2e.ti.com/.../426680

    BR
    Margarita
  • I have seen this spec you point out. My questions are
    1) To be clear, we are not using embedded syncs (SAV/EAV) but generating externals syncs in the FPGA connected to the TI chip. In Section 2.11 I do not see the use of the word DE or data enable. Our signal is coming in bursts i.e. we may have several cycles of "no data" and typically one would use the data enable to ignore the bytes which are not valid. I do see the DE pins in the data sheet so presumably those pins can be configured to capture date in bursts. My system runs the TI at a faster rate than the camera clock so we will have gaps in the data (even though the overall data rate will be correct). Since I do not have storage before the TI the question is
    can the chip use DE?

    We have not had much luck with D3 in terms of getting data sheets etc. Are there detailed specs that we can get from a support partner without having to generate a PO and paying for services (glad to do so if we need the help).

    2) We are using ezsdk version 5.04.00.11. Where in the SDK can we set the input to be YCbCr and perhaps change the polarity of the hsync/vsync and turn on data enable.