Part Number: TMDXEVM8148
Tool/software: Linux
The 8148 EVM is setup to run at 20 MHz. The platform I am developing on is using a 8127 running at 24 MHz.
What changes are required to support the higher frequency?
Also, there are discrepancies between GEL scripts and u-boot values.
Need to verify what the differences are?
I have some discrepancies with the DDR3 config, the initial values are not the same as the scripts. What values should be used and are they related to emif0 or emif1?
/* TI814X DDR3 PHY CFG parameters <emif0 : emif 1> */
#define DDR3_PHY_RD_DQS_CS0_BYTE0 ((emif == 0) ? 0x38 : 0x3A)
#define DDR3_PHY_RD_DQS_CS0_BYTE1 ((emif == 0) ? 0x37 : 0x36)
#define DDR3_PHY_RD_DQS_CS0_BYTE2 ((emif == 0) ? 0x32 : 0x37)
#define DDR3_PHY_RD_DQS_CS0_BYTE3 ((emif == 0) ? 0x31 : 0x33)
#define DDR3_PHY_WR_DQS_CS0_BYTE0 ((emif == 0) ? 0x43 : 0x49)
#define DDR3_PHY_WR_DQS_CS0_BYTE1 ((emif == 0) ? 0x44 : 0x4E)
#define DDR3_PHY_WR_DQS_CS0_BYTE2 ((emif == 0) ? 0x53 : 0x54)
#define DDR3_PHY_WR_DQS_CS0_BYTE3 ((emif == 0) ? 0x50 : 0x50)
#define DDR3_PHY_RD_DQS_GATE_CS0_BYTE0 ((emif == 0) ? 0xE4 : 0xD3)
#define DDR3_PHY_RD_DQS_GATE_CS0_BYTE1 ((emif == 0) ? 0x111 : 0xF7)
#define DDR3_PHY_RD_DQS_GATE_CS0_BYTE2 ((emif == 0) ? 0x112 : 0x109)
#define DDR3_PHY_RD_DQS_GATE_CS0_BYTE3 ((emif == 0) ? 0x13D : 0x135)
#define DDR3_PHY_WR_DATA_CS0_BYTE0 ((emif == 0) ? 0x85 : 0x8A)
#define DDR3_PHY_WR_DATA_CS0_BYTE1 ((emif == 0) ? 0x83 : 0x80)
#define DDR3_PHY_WR_DATA_CS0_BYTE2 ((emif == 0) ? 0x85 : 0x7F)
#define DDR3_PHY_WR_DATA_CS0_BYTE3 ((emif == 0) ? 0x7F : 0x85)
GEL:
#define DDR3_PHY_RD_DQS_CS0_DEFINE 0x30 // software leveling code @400MHz
#define DDR3_PHY_WR_DQS_CS0_DEFINE 0x21
#define DDR3_PHY_FIFO_WE_CS0_DEFINE 0xC0
#define DDR3_PHY_WR_DATA_CS0_DEFINE 0x44
Steve
