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AM5708: Tweaking the SPI clock

Blake Carpenter
Expert 6985 points
Part Number: AM5708

Hi,

My customer is trying to pull in exactly 50mhz worth of SPI readings to the C6xxx instead of the 48mhz limit currently on the SPI bus.

From pouring over the TRM and datasheet, TRM figure 24-82 shows the McSPI is sourced from PER_48M_GFCLK.

The datasheet table 5-9 shows the max allowed clock is 48mhz for PER_48M_GFCLK.

Any workaround you see?  Like tweaking the main clock up a hair to speed up all the generated clocks? 50/48 seems like a mild overdrive the customer MIGHT entertain.

Any other way pull in 50mhz of SPI data from a SPI peripheral rather than the 48MHz limit?

Perhaps using the PRU's as in TDA-01555?

Any suggestions would be appreciated.

Best Regards,

Blake

  • 0
    TI__Guru**** 393215 points
    Hi Blake,

    TI cannot recommend overriding the device specifications. The PRU approach might be possible, though I'm not sure if the 200MHz clock frequency of the PRU will allow enough margin for signal processing.
  • 0 in reply to Biser Gatchev-XID
    TI__Expert 6985 points
    Hi Biser,

    The Engineer notes that there are several integer frequencies he can use... some faster and some slower. He has tried non-integer's and they break his code. This is interesting because if we underdrive the part very slightly 997MHz... the DSP algorithm's work (assuming this cascades down to the 48MHz clock being slightly slower.

    From the TRM I didn't see any way to use an external clock to generate PER_48M_GFCLK to go slower than 48MHz, but slowing the system clock very slightly might work too... I see this causing issues with other systems like Ethernet, USB, and perhaps DDR timing, but to you think this is something that is worth exploring?

    Best regards, Blake
  • 0 in reply to Blake Carpenter
    TI__Guru**** 393215 points
    I don't understand. In your initial post you state you need 50MHz, and in your last post you state you need <48MHz. Which is true?
  • 0 in reply to Biser Gatchev-XID
    TI__Expert 6985 points

    HI Biser,

    Sorry, my description wasn't clear. 

    The customer is sampling an ADC.  They need to be on integer boundaries of a certain frequency for their software.  He initially concentrated at 50MHz which was a faster integer multiple.  However there are several slower than 48mhz frequencies that will work as well.    He currently is running at 50MHz SPI clock, but when he realized this was non-trivial since there was no external SPI frequency input (or easy way to speed it up), he threw out a couple of slower frequencies.  He can hit one if he adjusts the 1 GHz frequency of the processor down to 997MHz... which would adjust the 48MHz to slightly slower (I am guessing).

    Does this clear things up?

    Thanks!  Blake

  • 0 in reply to Blake Carpenter
    TI__Guru**** 393215 points
    I think I understand now. The DSP is clocked by a dedicated clock, DSP1_GFCLK, which is generated by the DPLL_DSP. This can be adjusted as necessary as long as below the DSP maximum frequency for the speed grade used.