Tool/software: TI-RTOS
Champs,
We've been debugging the following issue for a while and could use your advise
Customer's application calculates an array of data (an 1080x1920 frame) and sends it out over DSS (using DMA). At the end of the calculation Cache_wb() is invoked in order to make sure all the data is written back to the DDR and ready to be picked up and sent out. The "wait" parameter is "true" in order to ensure the data is valid in the DDR. This works most of the time. On occasion, some data in the DDR is found to be invalid (typically last column in the frame). In the course of debugging a piece of code has been added after the cache_wb() call that just reads the entire array and compares each pixel's value with a constant. Interestingly enough adding this piece of code makes the problem go away.
This suggests that the cache_wb() (despite having cache_wait() called) does not fully accomplish the write-back operation and by doing read over the whole array the data is finally making it back to the DDR. The read operation takes non-negligible amount of time and this puts a strain on the application, we would like to have this corrected.
Any insights you could provide will be greatly appreciated
regards
Michael
