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AMIC110: EtherCAT errata PINDSW-1531

Kanae
Guru 10225 points

Part Number: AMIC110
Other Parts Discussed in Thread: AM3357, AM3359, DP83848K-MAU-EK, TEST2


Hi Sitara support team,

I would like to know about "PINDSW-1531" in the EtherCAT_Slave_Errata_PINDSW_01_00_05.
processors.wiki.ti.com/.../EtherCAT_Slave_Errata_PINDSW_01_00_05.pdf

There is the following description.

• Conditions in which failures occur
– Case with Large TxPDO (2Kbytes) and RxPDO (5 bytes)

Does it mean that...
1. This will occur in the combination of Large TxPDO (2Kbytes) and RxPDO (5 bytes)
or
2. This will occur in case of the Large TxPDO (2Kbytes)
or
3. This will occur in case of the RxPDO (5 bytes)

If it will occur in case 3, is the RxPDO (5 bytes) correct value?

My customer took measureｓ to divide the frames from TxPDO: 1280 bytes and RxPDO: 1024 byte.
It reduced the failures occur ratio from 25% to 10%.
My customer needs to fix or reduce the failures as soon as possible.

Could I have the effective measures to reduce the failures?
How many bytes should be set for TxPDO and RxPDO?

Best regards,
Kanae

  • 0
    TI__Guru**** 393215 points
    The RTOS team have been notified. They will respond here.
  • 0 in reply to Biser Gatchev-XID
    Guru 10225 points

    Hi Biser,

    Thank you for quick reply.
    I expect to know the specific frame setting value for TxPDO and RxPDO.

    Best regards,
    Kanae 

  • 0 in reply to Kanae
    Guru 10225 points

    Hi Sitara RTOS team,

    Here is additional information.
    My customer is using the following two configurators, it divides the frame as follows.

    Configurators: Acontis's Configurator and Beckhoff's configurator

    【Frame Division】
    Frame1: Slave1 1280 byte
    Frame2: Slave2 600 byte

    It occurs the communication failures by ”Configuration mismatch” in the both configurators.
    Could you please let me know the correct frame configurations.

    Best regards,
    Kanae

  • 0 in reply to Kanae
    TI__Mastermind 40580 points
    Hi Kanae, do you have Master/slave logs, wiresharks, and a descriptions of your setup and how to reproduce the issue? .

    thank you,
    Paula
  • 0 in reply to Paula Carrillo
    Guru 10225 points

    Hi Paula,

    Thank you for your reply.

    Here is wiresharks log.

    bad_00001_20180502151639.zip

    WiresharkSniffer.pdf

    Other info that I asked my customer to send will be posted soon.

    Best regards,

    Kanae

  • 0 in reply to Kanae
    Guru 10225 points

    Hi Paula,

    Here are the main points of additiional information.

    *****
    // Slave Information
    Slave        Sitara SoC    PRU-ICSS    LRW Data Size
    Slave 1    AMIC110     V1.00.05        1280 bytes
    Slave 2    AM3357       V1.00.05          536 bytes

    // Master Information
    CPU Intel ATOM Baytrail E3845 4 core 1.9GB
    EtherCAT stack :   Acontis EcMaster V2.9.1.99

    // Network topology
    EcMaster - (Protcol analyer　TAP　A) - Slave 1 - (Protcol analyer　TAP　B) - Slave 2

    Port　0　:　TAP　A　EcMaster　->　 Slave 1
    Port　1　:　TAP　A　 Slave 1　->　EcMaster
    Port　2　:　TAP　B　 Slave 1　->　Slave 2
    Port　3　:　TAP　B　Slave 2　->  Slave 1

    EtherCAT Protcol analyer : NANL-B500G-RE (Hilscher)

    // The issue
    The bus scan of EcMaster is failed.
    Frequency of failure:    11.2%     ( 37 times error / 331 times try)

    // The explanation of WireShark Log
    No.1 - No.35768   the log of normaly communicaton status
               The power of all boards was powered off. 
               And, the power of all boards was powered on.
    No.35769-            the log of the issue of bus scan

    *****

    I have an additional question.

    Q. Is it effective to send the amount of the slave1 data and the slave2 data in reverse?

    Best regards,
    Kanae

  • 0 in reply to Kanae
    TI__Mastermind 40580 points

    Hi Kanae,  good timing, I was also sending you a message. About your question, I am a little confused what you mean by data in reverse? could you please elaborate the question?

    On the other hand, after discussing with a colleague we have some question, and tests that we would like you to do/answer:

    Issue EtherCAT Slave not forwarding frame from IN to OUT (after power OFF/ON)

    1) Is it possible to reproduce the issue using TI AMIC110 and AM3359 ICEv2 boards?

    2) Is it possible to change order of slaves first AM3357, then AMI110. See if the issue still happens?, and if it happens is still the first slave that fails? Can you also test with two AM3357 OR two AMIC110 without mixing the boards?

    3) We believe you are testing your own custom boards, if so, could you gave us a summary of changes between our reference EVM and your custom boards? Especially, interested on understanding changes on PHY (if any).

    4) Our understanding is that you have a modified acontis EC-Master, which includes a workaround for another issue.  Current issue (OUT port no forwarding after power ON/OFF) happened also without the EC-Master workaround? Have you tested it with other master?

    5) Could you explain us how is the procedure of power ON/OFF of your system? Are all the slaves in OP when the master send BRD datagram (network scan)?. More specifically, when the first slave fails, which state is it at?

    Thank you,

    Paula

  • 0 in reply to Paula Carrillo
    Guru 10225 points
    Hi Paula,

    Thank you for your reply!

    About my last question, is it effect to change as the following?

    from
    Slave 1 AMIC110 V1.00.05 1280 bytes
    Slave 2 AM3357 V1.00.05 536 bytes

    to
    Slave 1 AMIC110 V1.00.05 536 bytes
    Slave 2 AM3357 V1.00.05 1280 bytes

    I will ask my customer about your requests.

    In my first post of this thread, dou you think that this issue caused by PINDSW-1531,
    or there is another cause?
    I understand you keep checking this issue to find out the causes.
    However my customer would like to know your current opinion for reference.

    Best regards,
    Kanae
  • 0 in reply to Kanae
    Guru 10225 points
    Hi Paula,

    Here are the answers to your requests.

    1) I will answer this later.

    2) The result to change order of slaves first AM3357, then AMI110 is happened the issue at 127th times.
    It is not much of N numbers, the reproduced ratio reduces about 0.8% (1/127) .
    It happens is still the first slave that fails.
    // Slave Information
    Slave Sitara SoC PRU-ICSS LRW Data Size
    Slave 1 AM3357 V1.00.05 536 bytes
    Slave 2 AMIC110 V1.00.05 1280 bytes

    It is not possible to test with two AM3357 OR two AMIC110 without mixing the boards,
    because it needs to change the system in large scale.

    3) The custom boards is designed based on the EVM; DP83848K-MAU-EK.
    Their slave board is using DP83848KSQ/NOPB (TI).
    Customer's application is CPU board; ACONTIS master and the custom slave boards.

    4) Yes, the current issue (OUT port no forwarding after power ON/OFF) happened also
    without the EC-Master workaround.
    The results tested it with other masters are happened the issue.
    Master: Beckhoff's TWINCAT and ET9000 V2.11*
    *It happened at 12th times with ET9000 V2.11

    5) In test environment, the power of the Master, the slave1, and slave2 are turned on at the same time.
    There are time differences to be the ready status like the following.
    Master (CPU): approx. 40 seconds ← Timing of EcMaster to start the bus scan
    slave 1: approx. 10 seconds
    slave 2: approx. 10 seconds

    When the Ecmaser starts the bus scan, the slave 1 and 2 are ready to communicate.
    However, the BRD datagram (network scan) from the master has not arrived,
    it can not transition to the OP.

    Best regards,
    Kanae
  • 0 in reply to Kanae
    TI__Mastermind 40580 points
    Hi Kanae, We are working on reproducing the issue. Some questions:

    - Are you using EtherCAT ddrless version in AMIC110?
    - When you do Power Off/On test do you also power Off/On the Master? or only the slaves?
    - Which cycle time are you using?

    On the other hand, if you have had a chance to test using TI EVMs please let me know your results.

    Finally, could you also test disabling Enhanced link detection in the slaves?
    C:\TI\PRU-ICSS-EtherCAT_Slave_01.00.05.00\protocols\ethercat_slave\ecat_appl\EcatStack\tiescbsp.c: mdioParamsInit.enhancedlink_enable = TIESC_MDIO_RX_LINK_DISABLE


    Thank you,
    Paula
  • 0 in reply to Paula Carrillo
    Guru 10225 points

    Hi Paula,

    Thank you for your reply.

    Regarding the following question, this answer is in my last post #5).
     - When you do Power Off/On test do you also power Off/On the Master? or only the slaves?

    At the Powter Off/On test, the Master and the slaves are  powered Off/On at the same time.


    Other your questions/reuest will be asked to my customer.

    Best regards,
    Kanae

  • 0 in reply to Kanae
    TI__Mastermind 40580 points
    Hi Kanae, I got your private message, thanks for the information. We will continue working on reproducing the issue and working with the developers to rule it is not related to a previous fixed (reported) issue.

    One quick question, did you have the opportunity to test disabling Enhanced link?

    mdioParamsInit.enhancedlink_enable =
    TIESC_MDIO_RX_LINK_ENABLE;//TIESC_MDIO_RX_LINK_DISABLE;

    Thank you,
    Paula
  • 0 in reply to Paula Carrillo
    Guru 10225 points

    Hi Paula,

    The result of disabling link detection in the test, it is no effect with the coustomer test enviroment.

    The issue reproduced ratio is about 3 %.

    Could you please explain the reason to disable the enhanced link detection?

    Why do you think the measure will be effective? 

    Best regards,
    Kanae

  • 0 in reply to Kanae
    TI__Mastermind 40580 points
    Hi Kanae, thanks for the update.

    In the meantime, could you also help us to get wireshark logs in test1 when it fails, and icss memory dump (512KB address space) from CCS in a working and non-working setup for comparison?.

    About disabling Enhanced link detection, this test was proposed for ruling out a previous internal observation when developing AMIC110 with DP83822

    thank you,

    Paula
  • 0 in reply to Paula Carrillo
    Guru 10225 points
    Hi Paula,

    Thank you for your reply.

    I understand the reason to disable the Enhanced link detection.
    I will check to be able to get wireshark logs and icss memory dump in test1 when it fails,

    Best regards,
    Kanae
  • 0 in reply to Kanae
    TI__Mastermind 40580 points
    Hi Kanae, and also same logs when it works, so we can compare.

    thank you,
    Paula
  • 0 in reply to Paula Carrillo
    Guru 10225 points
    Hi Paula,

    I would like to check what you need the data.

    Test1 is not the customer test method.
    Test1 can be worked on disabling Enhanced link detection,
    however Test1 has issue on Enhanced link detection.

    Test2 is the customer test method.
    Test2 cannot be worked on both disabling and Enhanced link detection.

    Do you need the log data and memory dump for following four types each?

    1.Test1 on disabling Enhanced link detection
    2.Test1 on Enhanced link detection.
    3.Test2 on disabling Enhanced link detection.
    4.Test2 on Enhanced link detection.

    Best regards,
    Kanae
  • 0 in reply to Kanae
    TI__Mastermind 40580 points
    Hi Kanae, we need logs for your 4th option. Logs for the other options are optional.

    thank you,
    Paula
  • 0 in reply to Paula Carrillo
    Guru 10225 points

    Hi Paula,

    I sent you the data you requested by a private message.
    Please check them.

    Best regards,
    Kanae

  • 0 in reply to Kanae
    TI__Mastermind 40580 points
    Hi Kanae, thanks for the data. But it seems wiresharks are only taking when system is not working. We only see frames from master but not returned frames from slaves. Could you please help us to get a wireshark that shows the transition from working to no working?

    Also maybe good to add a Tap between Slave1 and Slave2? A similar topology as shown below:
    EcMaster - (Protcol analyer　TAP　A) - Slave 1 - (Protcol analyer　TAP　B) - Slave 2

    thank you,
    Paula
  • 0 in reply to Paula Carrillo
    Guru 10225 points

     

    Hi Paula,

     

    The date is at the issue happened, therefore it seems wiresharks are only taking when system is not working.

    I will get the new log including the transition from working to no working that might be big data

    and send you them by a private message later.

     

    It is difficult to add a Tap between Slave1 and Slave2 as you requested. 

    It might be possible to get the log between Slave1 and Slave2 separately.

     

    EcMaster - (Protcol analyer　TAP　A) - Slave 1 - (Protcol analyer　TAP　B) - Slave 2

     

    Best regards,

    Kanae

  • 0 in reply to Kanae
    TI__Mastermind 40580 points

    Hi Kanae, understood.

    thank you,

    Paula

  • 0 in reply to Paula Carrillo
    TI__Mastermind 40580 points
    Kanae, just want to confirm, latest shared data is for Test method 2 (re-starting master and slaves), right?
    Paula
  • 0 in reply to Paula Carrillo
    Guru 10225 points

    Hi Paula,

    Yes,  your understanding is right.

    Kanae

  • 0 in reply to Kanae
    TI__Mastermind 40580 points
    Hi Kanae, we got some test ideas from our development team. Could you please try the following:

    1.Disabling enhanced link detection by clearing bit in ESI EEPROM Word0. Bit9. Please test with and without MLINK mode (forwarding LED_LINK as link status).

    2. Test forcing 100 FD for all ports.

    Let me know if this is clear, or if you have any questions.
    thank you,
    Paula
  • 0 in reply to Paula Carrillo
    Guru 10225 points


    Hi Paula,

    Thank you for your reply.

    The test from your development team may take time.

    Now, have you progressed to reproduce the issue so far?
    Could you please inform us about the current reproduced test status?

    Best regards,
    Kanae

  • 0 in reply to Kanae
    Guru 10225 points

    Hi Paula,

    I would like to confirm the following your requests.

    #1. means the different procedure to be enable/disable enhanced link detection, right?
    The test with/without enhanced link detection changed by firm ware code have done so far.
    Does this request mean that enhanced link detection must be enable/disable by ESI setting?

    Regarding #2., could I have the specific procedure to force 100 FD for all ports
    for AM335x board and AMIC110 board, if they need some settings.

    Best regards,
    Kanae

  • 0 in reply to Kanae
    TI__Mastermind 40580 points
    Hi Kanae, apologize, I press "TI thinks Resolved" by mistake. I am working on reproducing the issue with some ideas from our developers. About your questions, I will confirm and be back to you.

    thank you,
    Paula
  • 0 in reply to Paula Carrillo
    TI__Mastermind 40580 points
    Hi Kanae,

    Q1.Yes, please also disable enhanced link detection in DL status register by setting ESI EPPEOM Word0.Bit9. You can update ESI XML following section to update EEPROM header <ConfigData>800EE088E8030000010000000000</ConfigData> to <ConfigData>800CE088E8030000010000000000</ConfigData>. Reload the ESI XML and program the EEPROM from TwinCAT

    Q2. I am double checking with the developers which is the right procedure. But one way is by setting /clearing some bits PHY BMCR register. Disabling AutoNeg, and then forcing 100M Full Duplex

    Hope this helps, Thank you,
    Paula
  • 0 in reply to Paula Carrillo
    Guru 10225 points
    Hi Paula,

    Thank you for your update and the answer.
    When you have the right procedure for #2 from the developers, please let me know.

    If you press "TI thinks Resolved" for this thread, can I keep to post here?

    Best regards,
    Kanae
  • 0 in reply to Kanae
    TI__Mastermind 40580 points
    Hi Kanae, do the slaves use DC mode? or not? Want to confirm.
    thank you,
    Paula
  • 0 in reply to Paula Carrillo
    Intellectual 435 points
    Hi Pauka -san,
    Q1 We sent 4patern of data
    > 1.Test1 on disabling Enhanced link detection
    > 2.Test1 on Enhanced link detection.
    > 3.Test2 on disabling Enhanced link detection.
    > 4.Test2 on Enhanced link detection.

    and we sent latest data yesterday.

    When customer disabling enhanced link detection ,they did update ESI XML to
    <ConfigData>800CE088E8030000010000000000</ConfigData>

    Thank you
    Akira
  • 0 in reply to Paula Carrillo
    Intellectual 435 points
    Hi Paula
    No,slaves don't use DC mode.

    Thank you
    Akira
  • 0 in reply to Akira555
    Guru 10225 points

    Hi Paula,

    I will send you sorting out your requests via "Private message".

    Best regards,
    Kanae

  • 0 in reply to Kanae
    TI__Mastermind 40580 points
    Hi Kanae and Akira, thank you for your feedback. We have done some progress reproducing the issue, and we are working on debugging it. We will keep you post it.

    thank you,
    Paula
  • 0 in reply to Paula Carrillo
    Guru 10225 points

    Hi Paula,

    Thank you for your update!

    I am waiting for your debug results.

    Best regards,
    Kanae

  • 0 in reply to Kanae
    TI__Mastermind 40580 points
    Hi Kanae, we have narrow down the issue, and created a firmware workaround. I just uploaded a .zip file to your server. Could you please generate app binaries including this new PRU-ICSS EtherCAT slave firmware and share them with us? In order to check if the workaround works OK.
    Thank you,
    Paula
  • 0 in reply to Paula Carrillo
    Guru 10225 points

    Hi Paula,

    Thank you for your reply and I have got your zip file.

    I will inform you the test results and I will share the app binaries including this new PRU-ICSS EtherCAT slave firmware later.

    Best regards,
    Kanae

  • 0 in reply to Kanae
    Guru 10225 points
    Hi Paula,

    I have uploaded the new firmware for your confirming to our server.
    This file is included only the first slave firmware.

    Best regards,
    Kanae
  • 0 in reply to Kanae
    TI__Mastermind 40580 points

    Hi Kanee, In order to close this thread, let me share here a workaround to the issue (MDIO sees link change, but INTC misses it). Please change MII Link from TYPE_EDGE to TYPE_PULSE.. Main idea here is if a condition arise where MDIOLINKINT is set and INTC SRSR is cleared, the SRSR should get set again due to the Level triggered mode.

    <PRU-ICSS-EtherCAT_Slave_PATH>\protocols\ethercat_slave\include\tiesc_pruss_intc_mapping.h

    #define PRU_ICSS1_INTC_INITDATA { \

    .....

    {MII_LINK0_EVENT, CHANNEL1, SYS_EVT_POLARITY_HIGH, SYS_EVT_TYPE_PULSE},\

    ....

    {MII_LINK1_EVENT, CHANNEL1, SYS_EVT_POLARITY_HIGH, SYS_EVT_TYPE_PULSE},\

    ....

    }

    thank you,

    Paula