Linux/DP83867CR: AM335x U-boot configuration

Hi Dharmesh,

It looks like you have questions about the AM335X SDK. I will move your thread to Sitara E2E forum for the correct visibility.

-Regards,
Aniruddha

Hi Dharmesh,

There is not an exact set of steps for each specific PHYs that maybe interfaced with the AM335x, including the ones TI sells in another division. But lets start with looking at the code where the setup takes place. There are not any PHY drivers used by the am335x here. Any necessary writes to the PHY are done using a miiphy_write call.

If you have review the u-boot code please take at look at this file board/ti/am335x/board.c and specifically the function board_eth_init(). This function will have to be modified to support your custom board. You will see board_is_ which are calls used to identify several TI boards. You will also see different places used to setup the RGMII phys that were used on the TI EVMs. This may or may not work for you. Please take and respond back here with additional questions.

Also please note that only interface is assumed/supported in u-boot. Is there a reason why you both interfaces?

Best Regards,
Schuyler

Hello Schuyler,

Thanks for your reply. In my custom board I have two NIC interface. At u-boot level I don't need both at same time. I wanted to use u-boot as board validation tool also. But it looks like u-boot may support only one NIC at a given time. that is OK.

Can i get some reference or sample code for initializing 10/100/1G for DP83867CR? Meanwhile i will do more digging in u-boot code.

Thanks,

Dharmesh.

Hi,

On my board I have two Phy (RGMII mode) mapped at address 0x0 and 0xF. part # DP83867CRRGZ.

But still link is not up. and here is my output for mdio and mii commands.

mdio list
cpsw:
0 - TI DP83867 <--> cpsw

mii info
PHY 0x00: OUI = 0x80028, Model = 0x23, Rev = 0x01, 10baseT, HDX
PHY 0x0F: OUI = 0x80028, Model = 0x23, Rev = 0x01, 10baseT, HDX

mii dump 0 0
0. (1140) -- PHY control register --
(8000:0000) 0.15 = 0 reset
(4000:0000) 0.14 = 0 loopback
(2040:0040) 0. 6,13 = b10 speed selection = 1000 Mbps
(1000:1000) 0.12 = 1 A/N enable
(0800:0000) 0.11 = 0 power-down
(0400:0000) 0.10 = 0 isolate
(0200:0000) 0. 9 = 0 restart A/N
(0100:0100) 0. 8 = 1 duplex = full
(0080:0000) 0. 7 = 0 collision test enable
(003f:0000) 0. 5- 0 = 0 (reserved)

mii dump 0 1
1. (7949) -- PHY status register --
(8000:0000) 1.15 = 0 100BASE-T4 able
(4000:4000) 1.14 = 1 100BASE-X full duplex able
(2000:2000) 1.13 = 1 100BASE-X half duplex able
(1000:1000) 1.12 = 1 10 Mbps full duplex able
(0800:0800) 1.11 = 1 10 Mbps half duplex able
(0400:0000) 1.10 = 0 100BASE-T2 full duplex able
(0200:0000) 1. 9 = 0 100BASE-T2 half duplex able
(0100:0100) 1. 8 = 1 extended status
(0080:0000) 1. 7 = 0 (reserved)
(0040:0040) 1. 6 = 1 MF preamble suppression
(0020:0000) 1. 5 = 0 A/N complete
(0010:0000) 1. 4 = 0 remote fault
(0008:0008) 1. 3 = 1 A/N able
(0004:0000) 1. 2 = 0 link status
(0002:0000) 1. 1 = 0 jabber detect
(0001:0001) 1. 0 = 1 extended capabilities

mii dump 0 2
2. (2000) -- PHY ID 1 register --
(ffff:2000) 2.15- 0 = 8192 OUI portion

mii dump 0 3
3. (a231) -- PHY ID 2 register --
(fc00:a000) 3.15-10 = 40 OUI portion
(03f0:0230) 3. 9- 4 = 35 manufacturer part number
(000f:0001) 3. 3- 0 = 1 manufacturer rev. number

mii dump 0 4
4. (01e1) -- Autonegotiation advertisement register --
(8000:0000) 4.15 = 0 next page able
(4000:0000) 4.14 = 0 (reserved)
(2000:0000) 4.13 = 0 remote fault
(1000:0000) 4.12 = 0 (reserved)
(0800:0000) 4.11 = 0 asymmetric pause
(0400:0000) 4.10 = 0 pause enable
(0200:0000) 4. 9 = 0 100BASE-T4 able
(0100:0100) 4. 8 = 1 100BASE-TX full duplex able
(0080:0080) 4. 7 = 1 100BASE-TX able
(0040:0040) 4. 6 = 1 10BASE-T full duplex able
(0020:0020) 4. 5 = 1 10BASE-T able
(001f:0001) 4. 4- 0 = 1 selector = IEEE 802.3

mii dump 0 5
5. (0000) -- Autonegotiation partner abilities register --
(8000:0000) 5.15 = 0 next page able
(4000:0000) 5.14 = 0 acknowledge
(2000:0000) 5.13 = 0 remote fault
(1000:0000) 5.12 = 0 (reserved)
(0800:0000) 5.11 = 0 asymmetric pause able
(0400:0000) 5.10 = 0 pause able
(0200:0000) 5. 9 = 0 100BASE-T4 able
(0100:0000) 5. 8 = 0 100BASE-X full duplex able
(0080:0000) 5. 7 = 0 100BASE-TX able
(0040:0000) 5. 6 = 0 10BASE-T full duplex able
(0020:0000) 5. 5 = 0 10BASE-T able
(001f:0000) 5. 4- 0 = 0 selector = ???

//-----------------------------------------------------------

Here is my code snippet from board.c

static void cpsw_control(int enabled)
{

return;

}

static struct cpsw_slave_data cpsw_slaves[] = {

{

.slave_reg_ofs = 0x208,

.sliver_reg_ofs = 0xd80,

.phy_addr = 0,

.phy_if = PHY_INTERFACE_MODE_RGMII,

},

{
.slave_reg_ofs = 0x308,
.sliver_reg_ofs = 0xdc0,
.phy_addr = 15,
.phy_if = PHY_INTERFACE_MODE_RGMII,
},

};

static struct cpsw_platform_data cpsw_data = {
.mdio_base = CPSW_MDIO_BASE,
.cpsw_base = CPSW_BASE,
.mdio_div = 0xff,
.channels = 8,
.cpdma_reg_ofs = 0x800,
.slaves = 2,
.slave_data = cpsw_slaves,
.ale_reg_ofs = 0xd00,
.ale_entries = 1024,
.host_port_reg_ofs = 0x108,
.hw_stats_reg_ofs = 0x900,
.bd_ram_ofs = 0x2000,
.mac_control = (1 << 5),
.control = cpsw_control,
.host_port_num = 0,
.version = CPSW_CTRL_VERSION_2,
};

int board_eth_init(bd_t *bis)
{
int rv, n = 0;

uint8_t mac_addr[6];
uint32_t mac_hi, mac_lo;

/*
* use efuse mac address for USB ethernet as we know that
* both CPSW and USB ethernet will never be active at the same time
*/
mac_lo = readl(&cdev->macid0l);
mac_hi = readl(&cdev->macid0h);
mac_addr[0] = mac_hi & 0xFF;
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
mac_addr[4] = mac_lo & 0xFF;
mac_addr[5] = (mac_lo & 0xFF00) >> 8;

if (!getenv("ethaddr"))
{
puts("<ethaddr> not set. Validating first E-fuse MAC\n");
if (is_valid_ethaddr(mac_addr))
eth_setenv_enetaddr("ethaddr", mac_addr);
}

writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);

cpsw_data.active_slave = 0; //PHY-1 - U43.
// cpsw_data.active_slave = 1; //PHY-2 - U44.

rv = cpsw_register(&cpsw_data);
if (rv < 0)
printf("Error %d registering CPSW switch\n", rv);
else
n += rv;

return n;

}

here is complete dump.

mii read 0 0-1f
addr=00 reg=00 data=1140
addr=00 reg=01 data=7949
addr=00 reg=02 data=2000
addr=00 reg=03 data=A231
addr=00 reg=04 data=01E1
addr=00 reg=05 data=0000
addr=00 reg=06 data=0064
addr=00 reg=07 data=2001
addr=00 reg=08 data=0000
addr=00 reg=09 data=0300
addr=00 reg=0a data=0000
addr=00 reg=0b data=0000
addr=00 reg=0c data=0000
addr=00 reg=0d data=0000
addr=00 reg=0e data=0000
addr=00 reg=0f data=3000
addr=00 reg=10 data=4040
addr=00 reg=11 data=0002
addr=00 reg=12 data=0000
addr=00 reg=13 data=0040
addr=00 reg=14 data=29C7
addr=00 reg=15 data=0000
addr=00 reg=16 data=0000
addr=00 reg=17 data=0040
addr=00 reg=18 data=6150
addr=00 reg=19 data=4040
addr=00 reg=1a data=0002
addr=00 reg=1b data=0000
addr=00 reg=1c data=0000
addr=00 reg=1d data=0000
addr=00 reg=1e data=0002
addr=00 reg=1f data=0000