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DM365 DDR2 IBIS Simulations



Hello All,

I am trying to verify SI performance on a layout for the DM365 processor.  While trying to get the simulations set up for the DDR2 interface,  I have ran across some issues that I think are rooted in the DM365 IBIS model.  Has any one come across any of these issues, and if so how did you handle them?

1) There are many available models for the DM365 DDR2 pins; however, only a few of them are defined as I/O buffers.

2)   I have simulated using both the NOSR0_NOTERM_1P8 and the SR0_NOTERM_1P8 models.  Both of these however seem to have incorrect thresholds defined (2V VinH on a 1.8V level signal).  Am I missing something, or is this just a mistake?

3) Many of the models (such as the two I mentioned above) have non-monotonic I-V curves for pullup/ pulldowns.   I manually eliminated the regions that were non-monotonic (since they were outside the range of IC operation). 

Are there any other pitfalls to look out for in this particular IBIS model?

Thanks,

Rick

  • 1) Choose the ones defined as I/O buffers for simulation

    2) The thresholds may need to be corrected in the models. However they are not useful for signal integrity purposes, which is all these models can be used for for DDR interfaces.

    3) The non-monotonicity in some curves is a known issue and is being fixed. But it shouldn't affect the simulation results.

    Jeff

  • JC,

    Can you elaborate on your response to item 2?  Why are the thresholds not useful for SI purposes? It seems like they are useful in determining how much crosstalk a particular layout may experience, and whether or not that crosstalk will cause issues.

    -Rick

     

  • You are right, it can help determine if there are any ripples near the logic thresholds. In the case of a discrepancy between the IBIS model and the datasheet values, always use what is found in the datasheet.

    Jeff