Hello All,
I am trying to verify SI performance on a layout for the DM365 processor. While trying to get the simulations set up for the DDR2 interface, I have ran across some issues that I think are rooted in the DM365 IBIS model. Has any one come across any of these issues, and if so how did you handle them?
1) There are many available models for the DM365 DDR2 pins; however, only a few of them are defined as I/O buffers.
2) I have simulated using both the NOSR0_NOTERM_1P8 and the SR0_NOTERM_1P8 models. Both of these however seem to have incorrect thresholds defined (2V VinH on a 1.8V level signal). Am I missing something, or is this just a mistake?
3) Many of the models (such as the two I mentioned above) have non-monotonic I-V curves for pullup/ pulldowns. I manually eliminated the regions that were non-monotonic (since they were outside the range of IC operation).
Are there any other pitfalls to look out for in this particular IBIS model?
Thanks,
Rick
 
				 
		 
					 
                           
				