Linux/PROCESSOR-SDK-AM335X: Changing McASP AHCLKX frequency

Tuan_Nguyen

Intellectual 680 points

Part Number: PROCESSOR-SDK-AM335X

Tool/software: Linux

Hi,

Currently, with oscilloscope, AHCLKX frequency approximate 24MHz. How could I change it to 26MHz.

I am using kernel 3.14

sys_clkin_ck: sys_clkin_ck {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
		ti,bit-shift = <22>;
		reg = <0x0040>;
	};
mcasp0_fck: mcasp0_fck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&sys_clkin_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

&mcasp0 {
        pinctrl-names = "default";
        pinctrl-0 = <&am335x_evm_audio_pins>;

        status = "okay";

        op-mode = <0>;          /* MCASP_IIS_MODE */
        tdm-slots = <2>;
        /* 4 serializers */
        serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
            0 0 1 2
        >;
        tx-num-evt = <1>;
        rx-num-evt = <1>;
};

sound {
		compatible = "ti,da830-evm-audio";
		ti,model = "AM335x-EVM";
		ti,audio-codec = <&tlv320aic3106>;
		ti,mcasp-controller = <&mcasp0>;
		ti,codec-clock-rate = <12000000>;
		ti,audio-routing =
			"Headphone Jack",       "HPLOUT",
			"Headphone Jack",       "HPROUT",
			"LINE1L",               "Line In",
			"LINE1R",               "Line In";
	};

Thanks

Tuan Nguyen

over 7 years ago

0 Biser Gatchev-XID over 7 years ago

TI__Guru**** 393215 points

What is the AHCLKX clock source? If it's internally generated it's derived directly from the OSC0 clock. In your case OSC0 is probably 24MHz. You will need to change the crystal for OSC0 to 26MHz. I cannot say how this will affect other peripherals you have.

0 Tuan_Nguyen over 7 years ago in reply to Biser Gatchev-XID

Intellectual 680 points

Hi Biser,

1/ How to check its internally generated from the OSC0 clock?
2/ When I try to divide AHCLKX to 12MHz, I set bit 1 in register AHCLKXCTL (B4), when I play a mp3 file (by mpg123 command tool), It's ok, but when I try to record, the AHCLKX clock still 24 MHz, still set bit 1 in register AHCLKXCTL (B4). (View in oscilloscope)
Did I miss somethings?

0 Pavel Botev over 7 years ago in reply to Tuan_Nguyen

TI__Guru**** 170625 points

Tuan,

Please provide the values of the below McASP registers fon analysis:

PFUNC
PDIR
AHCLKXCTL

Regards,
Pavel

0 Tuan_Nguyen over 7 years ago in reply to Pavel Botev

Intellectual 680 points

Hi Pavel,

PFUNC = 0
PDIR = 0x08000001
AHCLKXCTL = 0x8001

I found that when I record a file, TX is not controlled so I tried to set bit AFSRE in AFSRCTL Register and record is work well.
after that I found the XGBLCTL = 0x131F

Is it correct when I tried to sync receive and transmit clock?

Thanks

Tuan Nguyen

0 Pavel Botev over 7 years ago in reply to Tuan_Nguyen

TI__Guru**** 170625 points

Tuan_Nguyen said:
PFUNC = 0
PDIR = 0x08000001
AHCLKXCTL = 0x8001

This means your AHCLKX clock is internally generated:

PDIR[27] AHCLKX = 1 - Pin functions as output

AHCLKXCTL[15] HCLKXM = 1 - Internal transmit high-frequency clock source from output of programmable high clock divider

As Biser explained, your only option is to change Main Oscillator OSC0 from 24MHz to 26MHz.

I will check your other question and come back to you.

Regards,
Pavel

0 Pavel Botev over 7 years ago in reply to Tuan_Nguyen

TI__Guru**** 170625 points

Tuan_Nguyen said:
I found that when I record a file, TX is not controlled

Yes, during recording, only receive section of McASP is working.

Tuan_Nguyen said:
I tried to set bit AFSRE in AFSRCTL Register

There is no such bit as AFSRE, please double check.

Tuan_Nguyen said:
Is it correct when I tried to sync receive and transmit clock?

It depends on your use case. For receive only use case, I do not think you should sync receive and transmit clocks. You will need to sync rx to tx in loopback mode.

The McASP consists of transmit and receive sections that may operate synchronized, or completely independently with separate master clocks, bit clocks, and frame syncs, and using different transmit modes with different bit-stream formats. The McASP module also includes serializers that can be individually enabled to either transmit or receive.

The McASP clock generators are able to produce two independent clock zones: transmit and receive clock zones. The serial clock generators may be programmed independently for the transmit section and the receive section, and may be completely asynchronous to each other.

In loopback mode, the transmit clock and frame sync are used by both the transmit and receive sections of the McASP. The transmit and receive sections operate synchronously.

Regards,
Pavel

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Linux/PROCESSOR-SDK-AM335X: Changing McASP AHCLKX frequency