AM3357: On-chip memory specifications

Kaka

Part Number: AM3357

Hi TI Exports.

Please let me confirm the following question.
[Question]
Would you please teach me the access bit width and access speed?

AM335x:
ARM L1: Width/Speed
ARM L2: Width/Speed
On-chip-memory: Width/Speed

Best regards.
Kaka

over 7 years ago

0 Biser Gatchev-XID over 7 years ago

TI__Guru**** 393215 points

Hi,

For caches please read section 3.1.1 of the AM335x TRM Rev. P. Both caches are inside the ARM core and operate at the ARM frequency.
For OCMC RAM please read section 7.2.1 of the TRM. This memory operates at L3 frequency (200MHz).

0 Kaka over 7 years ago in reply to Biser Gatchev-XID

Guru 24520 points

HI biser

THANK YOU FOR YOUR RESPONSE.

How about bit width of each cache and memory?

Best regards.

Kaka

0 Biser Gatchev-XID over 7 years ago in reply to Kaka

TI__Guru**** 393215 points

From TRM:

– L1 Instruction and Data Cache of 32KB, 4-way, 16-word line with 128-bit interface.
– Integrated L2 cache of 256 KB, 8-way, 16 word line, 128 bit interface to L1 along with ECC/Parity supported.

Again, from TRM:

The on-chip memory controller consists of two separate modules that are OCP to memory wrappers. The first wrapper is for a ROM; the second is for a RAM. Each wrapper has its own dedicated interface to the L3 interconnect.
• 32- or 64-bit width

0 Kaka over 7 years ago in reply to Biser Gatchev-XID

Guru 24520 points

Hi Biser,

Thanks.
By the way, I heard that the Sitara need to have some cycles to access the L2 caches. So, the access speed will be slower than ARM frequency.
What do you think?

Best regards.
Kaka

0 JJD over 7 years ago in reply to Kaka

TI__Guru* 92350 points

Kaka, yes, there will be some latency associated with L2 cache. Please refer to the documentation on the Cortex-A8 on the ARM website if you need more details.

Regards,
James

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AM3357: On-chip memory specifications