AM5726: On-chip memory specifications

For caches please read section 4.1.2 of the AM572x TRM Rev. J. Both caches are inside the ARM core and operate at the ARM frequency.
For OCMC RAM please read section 15.6.1 of the TRM. This memory operates at L3 frequency (266MHz).
For IPU cache please read section 7.1.2 of the AM572x TRM Rev. J. Cache is inside the IPU core and operate at it's frequency.

Yes, GPMC total memory size is 512MB, with a maximum of 256MB possible on one chip select.

Kaka-san

In addition to the TRM , the following application note , Table 4 has a good summary 

This application note is for the DRA family of devices, but applies to AM57x family too.

Regards

Mukul