AM5726: ELM register indexing

UNA

Part Number: AM5726
Other Parts Discussed in Thread: SYSCONFIG

Hi,

I have question about ELM registers for AM5726.
In TRM, "i" is written in the following register and bit field. Does this indicate the chip select number of the GPMC to which the NAND is connected?

ELM_SYNDROME_FRAGMENT_*_i
ELM_IRQENABLE.LOCATION_MASK_i bit
ELM_IRQSTATUS.LOC_VALID_i bit
ELM_LOCATION_STATUS_i
ELM_ERROR_LOCATION_*_i

For example, if I want to connect NAND memory to the chip select number 2 of GPMC, should I use the following registers?

ELM_SYNDROME_FRAGMENT_*_2
ELM_IRQENABLE.LOCATION_MASK_2 bit
ELM_IRQSTATUS.LOC_VALID_2 bit
ELM_LOCATION_STATUS_2
ELM_ERROR_LOCATION_*_2

Best regards,
H.U

over 7 years ago

0 Biser Gatchev-XID over 7 years ago

TI__Guru**** 393215 points

Hi,

This is not correct. i is the syndrome polynomial number, where i = 0 to 7. This is explained in TRM section 15.5.4. There are no separate ELM instances for different CS.

0 UNA over 7 years ago in reply to Biser Gatchev-XID

Mastermind 7980 points

Hi Biser,

For example, about the setting method of "ELM_SYNDROME_FRAGMENT_ 0 _ i" is described in the API document of PDK as following.

file:///C:/ti/pdk_am57xx_1_0_9/packages/ti/csl/docs/doxygen/html/elm_8h.html

It seems that your document states that "i" specifies chip select. Is my understanding incorrect?

Best regards,

H.U

0 Steve Kipisz over 7 years ago in reply to UNA

TI__Genius 15510 points

I have asked the RTOS folks to look at their code. This is how Linux defines the registers
struct elm_registers {
u32 elm_irqenable;
u32 elm_sysconfig;
u32 elm_location_config;
u32 elm_page_ctrl;
u32 elm_syndrome_fragment_6[ERROR_VECTOR_MAX];
u32 elm_syndrome_fragment_5[ERROR_VECTOR_MAX];
u32 elm_syndrome_fragment_4[ERROR_VECTOR_MAX];
u32 elm_syndrome_fragment_3[ERROR_VECTOR_MAX];
u32 elm_syndrome_fragment_2[ERROR_VECTOR_MAX];
u32 elm_syndrome_fragment_1[ERROR_VECTOR_MAX];
u32 elm_syndrome_fragment_0[ERROR_VECTOR_MAX];
};

So it is not chip select.

Steve K.

0 Rahul Prabhu over 7 years ago in reply to Steve Kipisz

TI__Guru** 116170 points

Sorry for the delayed reply here, I have confirmed what Steve has reported here: the csNum parameter for all the devices is set to 0. The CSL is generated from the original IP spec which seems to have provision for multiple chipselect but all sitara devices and K2G device that contains GPMC and ELM module supports only csNum=0.

Regards,
Rahul

0 UNA over 7 years ago in reply to Rahul Prabhu

Mastermind 7980 points

Hi Rahul,

It seems that "csNum" of CSL's ELM API indicates "i" of ELM registers as I mentioned earlier.
Are you say that the NAND memory must be connected to the chip select 0 ( i = 0 ) for AM5726?

Best regards,
H.U

0 UNA over 7 years ago in reply to UNA

Mastermind 7980 points

Hi Rahul,

I am still expecting your response regarding above question.

Best regards,

H.U

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AM5726: ELM register indexing