Hi to everybody,
I have a question regarding doc SPRAAL6A (DDR2 pcb layout). On page 5 it says that parammeter Zo must be between 50-75 Ohms and the impedance control must be from Zo-5 to Zo+5. Does this mean that if DDR_ZN and DDR_ZP resistances are 200 ohm (as in the reference design), then Zo is 50 and, therefore, yo have to design all your DDR signal traces so that they all have an impedance bettween 45 and 55 ohms?
Thanks in advance,
Nuba.