Other Parts Discussed in Thread: TPS51200
My case detail as below:
1. I have use the TI DDR3 PHY Calc v11.xlsx calculate the Leveling CFG and put into my CCS Project.(Attached)
2. The SDRAM IC Manufacture PN is: MT41K256M16HA-125(we use 1.5V mode so we refer to : MT41J256M16HA-125 datasheet)
So we select MT41J256M16 15E(1333) in TI DDR3 Register Calc v4.xlsx as below.(Attached)
3. Our DDR3 reference Clock is 100MHz, so our 1333 DDR PLL setting is: M= 40, D=3.
Test case and result as below:
1. GEL file Test:
DDR3 value before test
After cfg complete, we will write all zero into 0x80000000~0x800000FF and read back to compare.
From the result, it seems some address can write successfully, and some can not.
C66xx_0: GEL Output: Global Default Setup...
C66xx_0: GEL Output: C6678L GEL file Ver is 1.5
C66xx_0: GEL Output: Setup Cache...
C66xx_0: GEL Output: L1P = 32K
C66xx_0: GEL Output: L1D = 32K
C66xx_0: GEL Output: L2 = ALL SRAM
C66xx_0: GEL Output: Setup Cache... Done.
C66xx_0: GEL Output: PLL1 Setup...
C66xx_0: GEL Output: PLL1 Setup for DSP @ 1000.0 MHz.
C66xx_0: GEL Output: SYSCLK2 = 333.3333 MHz, SYSCLK5 = 200.0 MHz.
C66xx_0: GEL Output: SYSCLK8 = 15.625 MHz.
C66xx_0: GEL Output: PLL1 Setup... Done.
C66xx_0: GEL Output: Power on all PSC modules and DSP domains...
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=2, md=9!
C66xx_0: GEL Output: Power on all PSC modules and DSP domains... Done.
C66xx_0: GEL Output: PA PLL is using SYSCLK/ALTCORECLK as the input
C66xx_0: GEL Output: PA PLL is in PLL mode
C66xx_0: GEL Output: PA PLL fixed output divider = 2
C66xx_0: GEL Output: PA PLL programmable multiplier = 21
C66xx_0: GEL Output: PA PLL programmable divider = 1
C66xx_0: GEL Output: the output frequency should be 10 times the PA reference clock
C66xx_0: GEL Output: configSGMIISerdes Setup... Begin
C66xx_0: GEL Output:
SGMII SERDES has been configured.
C66xx_0: GEL Output: Enabling EDC ...
C66xx_0: GEL Output: L1P error detection logic is enabled.
C66xx_0: GEL Output: L2 error detection/correction logic is enabled.
C66xx_0: GEL Output: MSMC error detection/correction logic is enabled.
C66xx_0: GEL Output: Enabling EDC ...Done
C66xx_0: GEL Output: Configuring CPSW ...
C66xx_0: GEL Output: Configuring CPSW ...Done
C66xx_0: GEL Output: DDR begin (1333 auto)
C66xx_0: GEL Output: XMC Setup ... Done
C66xx_0: GEL Output:
DDR3 PLL initialization is complete.
C66xx_0: GEL Output:
DDR3 1333MHz initialization is complete.
C66xx_0: GEL Output: DDR3 memory all zero test... Started
C66xx_0: GEL Output: DDR3 memory all zero test... Failed
C66xx_0: GEL Output: DDR done
C66xx_0: GEL Output: Global Default Setup... Done.
Memory result after first time run memory test:
If I trig write once more, some more address will be wrote successfully but still some fail.
If I manually input value(AAAA5555 or others) in the memory browser, it can write and read back successfully.
Attached is my Calc setting, my Keystone_DDR_Init,c and My gel file.
Please help comment what maybe the problem?
And What can I do now to trouble shoot?
Thanks a lot
