This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TDA3XEVM: TMS320C64x+ DSP cache configuration

Part Number: TDA3XEVM
Other Parts Discussed in Thread: SYSBIOS

Hi,

I am doing a monitoring function to monitor the dsp cache configuration.

By reading through the memory browser, I figure out our current system dsp cache configuration as follow:

I checked app.cfg and I only found ti_sysbios_family_c66p_Cache.initSize.l2Size = ti_sysbios_family_c66p_Cache.L2Size_128K which configure the L2 cache.


I cannot seem to figure out where we are configuring L1D and L1P cache. Can I know what are the ways to configure DSP cache?

  • Hi Myat,

    The default behavior, when DSP is pulled out of reset, is that the L1P and the L1D caches are on and their size is set to 32 KB. The init size from BIOS is also set in the same way: bios_X_XX_XX_XX\packages\ti\sysbios\family\c66\Cache.xdc

    /*! Default sizes of caches.

    * @_nodoc
    */
    config Size initSize = {
    l1pSize: L1Size_32K,
    l1dSize: L1Size_32K,
    l2Size: L2Size_0K
    };

    Thanks and Regards,

    Piyali