AM3352: GPIO drives low PMIC reset input

Takanori Yuzawa

Part Number: AM3352

Hi team

When connect to RESET pin on PMIC and GPIO on CPU then voltage level for RESET pin is 0.9V and PMIC does not work correctly.
It seems that GPIO on AM3352 drives low. Do you have any advice?

Best Regards,
Takanori Yuzawa

AM3352 circuit.xlsx

Waveforms of PMIC_RESETn and GPIO2_0.pptx

over 7 years ago

0 Biser Gatchev-XID over 7 years ago

TI__Guru**** 393215 points

What is the VDDSHVx voltage from which the GPIO is powered?

0 Takanori Yuzawa over 7 years ago in reply to Biser Gatchev-XID

TI__Intellectual 1490 points

All VDDSHVx are supplied 3.3V.

0 Biser Gatchev-XID over 7 years ago in reply to Takanori Yuzawa

TI__Guru**** 393215 points

All GPIO signals are in an undetermined state until processor supplies have fully ramped-up and stabilized.

0 Takanori Yuzawa over 7 years ago in reply to Biser Gatchev-XID

TI__Intellectual 1490 points

AM3352 does not work correctly during ramping up because nRESET is asserted.
Please see the wave form below.
When PMIC_PWR_EN is asserted then VDDSH is 0V for a little time and GPIO2_0 seems to be pulled to 0V.
For this reason, GPIO2_0 (nRESET) is low level then PMIC does not work correctly.

Best Regards,
Takanori Yuzawa

0 Biser Gatchev-XID over 7 years ago in reply to Takanori Yuzawa

TI__Guru**** 393215 points

There is no picture in your post.

0 Takanori Yuzawa over 7 years ago in reply to Biser Gatchev-XID

TI__Intellectual 1490 points

Please see again.

0 Biser Gatchev-XID over 7 years ago in reply to Takanori Yuzawa

TI__Guru**** 393215 points

What I see in this picture is perfectly normal behavior. You are holding the PMIC in reset and it cannot properly execute the power-on sequence. This is an incorrect use case and you should design some other way to reset the PMIC if this is really necessary.

0 Takanori Yuzawa over 7 years ago in reply to Biser Gatchev-XID

TI__Intellectual 1490 points

CPU accesses nRESET on PMIC directory is incorrect use?
And also, please let me know how to prevent such kind of behavior.

Best Regards,
Takanori Yuzawa

0 Biser Gatchev-XID over 7 years ago in reply to Takanori Yuzawa

TI__Guru**** 393215 points

Yes, in my opinion this is not correct. You are creating an endless loop in this way. You should design some external circuitry that will isolate the PMIC reset input from the GPIO output until the processor has started properly.

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AM3352: GPIO drives low PMIC reset input