Hello,
I am trying to access (cacheable) the first 2MBs of MSMC using the ARM cores. The rest, 4MB is configured as non-cacheable access.
My MMU configuration is:
//Cacheable 2MBs
var attrs = new Mmu.DescriptorAttrs();
Mmu.initDescAttrsMeta(attrs);
attrs.type = Mmu.DescriptorType_BLOCK;
attrs.shareable = 3;
attrs.attrIndx = 2;
Mmu.setMAIRMeta(2, 0xFF);
for (var i=0x0c000000; i<0x0c200000; i=i+0x00200000) {
Mmu.setSecondLevelDescMeta(i, i, attrs);
}
//Non-Cacheable 4MBs
var attrs2 = new Mmu.DescriptorAttrs();
Mmu.initDescAttrsMeta(attrs2);
attrs2.type = Mmu.DescriptorType_BLOCK;
attrs2.attrIndx = 0;
Mmu.setMAIRMeta(0, 0x44);
for (var i=0x0c200000; i<0x0c600000; i=i+0x00200000) {
Mmu.setSecondLevelDescMeta(i ,i, attrs2);
}
My example of usage is:, fill some descriptors which are mapped to the cacheable 2MBs, do cache write-back, then do memory barrier and finally push the descriptor to the qmss que. The descriptors in the que are popped by DSPs, following a cache invalidation.
The problem is, DSP can read false data. However, using the entire same code, when the descriptors are mapped to the cacheable DDR, DSP always reads the correct data.
What may cause this? Is there any configuration specific requirement for the cacheable MSMC usage by the ARM?
Thank you very much,
Erman