AM3354: DDR3 configuration

but ，when cpu is working，how many rowbits that it will operate。

thanks for your reply，but I could not find the real data n TRM 。

and only in EBANK=0,IBNAK=0,PAGESIZE=0,ti tells me the row address is 15bits.And other situation ,I still could not kown the row address value

thanks for you reply

my ddr is use A0-A15 row address bus，and it can run  normally，but I find my uboot set the row size is 15bits，of course this setting is not in effect。because ibank_pos is set to 0,and reg_ebank_pos also set to 0,and pagesize is set to2.

#define DDR3_EMIF_SDCFG			       0x61C04B32
#define EMIF4_0_SDRAM_CONFIG            (EMIF4_0_CFG_BASE + 0x08)
#define EMIF4_0_CFG_BASE		0x4C000000

writel(DDR3_EMIF_SDCFG, EMIF4_0_SDRAM_CONFIG);

.so I have a question , row address is empty according to the Table 7-100 in TRM,why the ddr3 is still can run normally.

thanks.