TMDSICE3359: ICSS EMAC issue

Dawid Balcerzak

Part Number: TMDSICE3359
Other Parts Discussed in Thread: AM3359

Hello,

I am new to Sitara processors but I am tryging to learn a bit. According to my previus posts on e2e forum and help I received I prepared examples by clicking "pdkProjectCreate.bat" in ti\pdk_am335x_1_0_10\packages. I tried some of them and they compile and run correct, e.g. in UART or GPIO examples I had "All tests have passed" in PuTTy.

My goal is an Ethernet connection with another device (PC or another TI board) so I tried 'ICSS_EMAC_BasicExample_icev2AM335x_wSoCFile_armTestproject'. It's compiled fine, but in console I haven't got "All tests have passed" info (but I should according to

I loopbacked Ethernet ports and here is my PuTTy log:

ICSS_EMAC_testDrvInit: instance: 1, data0RamSize: 0x2000, data1RamSize: 0x2000, sharedDataRamSize: 0x3000, l3OcmcSize: 0x10000
ICSS_EMAC_testDrvInit: instance: 1, data0RamSize: 0x2000, data1RamSize: 0x2000, sharedDataRamSize: 0x3000, l3OcmcSize: 0x10000
Validate Firmware: Release1: 0x11, Release2: 0x85010004
ICSS_EMAC_testTaskPruss1: LINK IS DOWN,skipping PRU1 ETH0
ICSS_EMAC_testTaskPruss1: LINK IS DOWN,skipping PRU1 ETH0
ICSS_EMAC_testTaskPruss1: LINK IS DOWN,skipping PRU1 ETH0
ICSS_EMAC_testTaskPruss1: LINK IS DOWN,skipping PRU1 ETH0
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ICSS_EMAC_testTaskPruss1: LINK IS DOWN,skipping PRU1 ETH0
ICSS_EMAC_testTaskPruss1: LINK IS DOWN,skipping PRU1 ETH0
ICSS_EMAC_testTaskPruss1: LINK IS DOWN,skipping PRU1 ETH0
ICSS_EMAC_testTaskPruss1: LINK IS DOWN,skipping PRU1 ETH0
ICSS_EMAC_testTaskPruss1: LINK IS DOWN,skipping PRU1 ETH0
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ICSS_EMAC_testTaskPruss1: LINK IS DOWN,skipping PRU1 ETH0
ICSS_EMAC_testTaskPruss1: LINK IS DOWN,skipping PRU1 ETH0
ICSS_EMAC_testTaskPruss1: LINK IS DOWN,skipping PRU1 ETH0
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ICSS_EMAC_testTaskPruss1: LINK IS DOWN,skipping PRU1 ETH0
ICSS_EMAC_testTaskPruss1: LINK IS DOWN,skipping PRU1 ETH0
ICSS_EMAC_testTaskPruss1: LINK IS DOWN,skipping PRU1 ETH0
ICSS_EMAC_testTaskPruss1: LINK IS DOWN,skipping PRU1 ETH0
ICSS_EMAC_testTaskPruss1: LINK IS DOWN,skipping PRU1 ETH0
ICSS_EMAC_testTaskPruss1: LINK IS DOWN,skipping PRU1 ETH0
ICSS_EMAC_testTaskPruss1: LINK IS DOWN,skipping PRU1 ETH0
ICSS_EMAC_testTaskPruss1: LINK IS DOWN,skipping PRU1 ETH0
ICSS_EMAC_testTaskPruss1: LINK IS DOWN,skipping PRU1 ETH0
ICSS_EMAC_testTaskPruss1: LINK IS DOWN,skipping PRU1 ETH0
ICSS_EMAC_testTaskPruss1: LINK IS DOWN,skipping PRU1 ETH0
ICSS_EMAC_testTaskPruss1: LINK IS DOWN,skipping PRU1 ETH0
ICSS_EMAC_testTaskPruss1: LINK IS DOWN,skipping PRU1 ETH0
ICSS_EMAC_testTaskPruss1: LINK IS DOWN,skipping PRU1 ETH0
ICSS_EMAC_testTaskPruss1: LINK IS DOWN,skipping PRU1 ETH0
ICSS_EMAC_testTaskPruss1: LINK IS DOWN,skipping PRU1 ETH0
ICSS_EMAC_testTaskPruss1: LINK IS DOWN,skipping PRU1 ETH0
ICSS_EMAC_testTaskPruss1: LINK IS DOWN,skipping PRU1 ETH0
ICSS_EMAC_testTaskPruss1: LINK IS DOWN,skipping PRU1 ETH0
ICSS_EMAC_testTaskPruss1: LINK IS DOWN,skipping PRU1 ETH0
ICSS_EMAC_testTaskPruss1: LINK IS DOWN,skipping PRU1 ETH0
ICSS_EMAC_testTaskPruss1: LINK IS DOWN,skipping PRU1 ETH0
ICSS_EMAC_testTaskPruss1: LINK IS DOWN,skipping PRU1 ETH0
ICSS_EMAC_testTaskPruss1: LINK IS DOWN,skipping PRU1 ETH0
ICSS_EMAC_testTaskPruss1: LINK IS DOWN,skipping PRU1 ETH0
ICSS_EMAC_testTaskPruss1: LINK IS DOWN,skipping PRU1 ETH0
ICSS_EMAC_testTaskPruss1: LINK IS DOWN,skipping PRU1 ETH0
ICSS_EMAC_testTaskPruss1: LINK IS DOWN,skipping PRU1 ETH0
ICSS_EMAC_testTaskPruss1: LINK IS DOWN,skipping PRU1 ETH0
ICSS_EMAC_testTaskPruss1: LINK IS DOWN,skipping PRU1 ETH0
ICSS_EMAC_testTaskPruss1: LINK IS DOWN,skipping PRU1 ETH0
ICSS_EMAC_testTaskPruss1: LINK IS DOWN,skipping PRU1 ETH0
ICSS_EMAC_testTaskPruss1: LINK IS DOWN,skipping PRU1 ETH0
ICSS_EMAC_testTaskPruss1: LINK IS DOWN,skipping PRU1 ETH0
ICSS_EMAC_testTaskPruss1: PRU1 ETH0: LINK IS UP, eth0 state: 1



============================================================
 ICSS_EMAC_testTaskPruss1: Testing NonPromiscuous Mode
 sending Unicast packets as destination address == eth own address
============================================================

To be honest I am not sure what's this about but it's definietely not correct.

Do you have some ideas what should I check first? I didn't do any changes in code, I ran it as-is.

I appreciate any help.

BR,
Dawid.

--- Edit ---

I changed destination address in ICSS_EMAC_testPkt[] on my PC MAC address and result is the same. Moreover, Wireshark shows nothing. Tx is broken?

--- Edit2 ---

Is it possible to run Ethernet using API on bare-metal applications?

over 7 years ago

0 Dawid Balcerzak over 7 years ago

Expert 1365 points

I asked about bare-metal application because I don't need RTOS actually, at the beginning I would be satisfied with as simplest as possible Tx and Rx application using raw Ethernet frames. It would be great starting point to more complex applications.

0 Biser Gatchev-XID over 7 years ago in reply to Dawid Balcerzak

TI__Guru**** 393215 points

The RTOS team have been notified. They will respond here.

0 Dawid Balcerzak over 7 years ago in reply to Biser Gatchev-XID

Expert 1365 points

In the meantime I managed with transceving data and finally I succeeded. I just changed Tx task on my own, here it is:

int32_t retvalTx;
Void taskSendPacket(UArg a0, UArg a1)
{

    ICSS_EmacTxArgument txArgs;
    txArgs.icssEmacHandle = ICSS_EMAC_testHandle;
    txArgs.lengthOfPacket = ETHERNET_FRAME_SIZE_64;
    txArgs.portNumber = 1;
    txArgs.queuePriority = 3;
    txArgs.srcAddress = &dummyPkt[0];

  //wait for system to initialize
  //Send packet in a loop every 500ms
  //Task_sleep(5);
  while(1) {
    //Send packet on PORT 1*. Size is known previously
    retvalTx = ICSS_EmacTxPacket(&txArgs, NULL);
    //Task_sleep(5);
  }
}

It works. RetvalTx is 0 and I can see packets in Wireshark on my PC. In Statistics I can see that average speed is 44 Mbits. It's far away from ~ 90 Mbits - on TI wiki sources I found that these Ethernet controllers should work with about 94 Mbits. I checked clock cycles between ICSS_EmacTxPacket calls and it is about 20700:

With 200 MHz clock, 20786 cycles took 103,93 us. Sending 159 bytes (it is my frame length) takes about 13 us with 100 Mbit speed. Delays in my application are a little bit too big I think. Am I doing someting wrong or I should change something with configuration to decrease them?

--- EDIT ---

In BIOS cfg I found that:

So - Is my AM3359 working with 550 MHz clock? I know that max. clock for AM3359 is 800 MHz but I don't know if I can set it in BIOS cfg 'just like that' and I don't know if Ethernet peripheral has another clock source. I don't know if clock set in platform settings is changed by this line:

Board_initCfg cfg = BOARD_INIT_PLL| BOARD_INIT_MODULE_CLOCK |  BOARD_INIT_DDR | BOARD_INIT_ICSS_PINMUX | BOARD_INIT_UART_STDIO | BOARD_INIT_ICSS_ETH_PHY;

0 Garrett Ding over 7 years ago in reply to Dawid Balcerzak

TI__Mastermind 43296 points

Dawid,

Have you tried to increase the payload size from ETHERNET_FRAME_SIZE_64 to ETHERNET_FRAME_SIZE_1518? The 94Mbps should be measured with a larger payload.

With default GEL configure - hotmenu ARM_OPP100_Config()

{

GEL_TextOut("**** AM335x ALL PLL Config for OPP == OPP100 is in progress ......... \n","Output",1,1,1);

GetInputClockFrequency();

if(CLKIN==24)

{

MPU_PLL_Config( CLKIN, 23, 600, 1);

....

You can update the CPU clock frequency to 600MHz from the GUI or BIOS.cpuFreq.lo = 600000000; in the cfg file.

Regards,

Garrett

0 Dawid Balcerzak over 7 years ago in reply to Garrett Ding

Expert 1365 points

Garrett,

thank you for the reply. I've just tried increasing frame size to 1518 bytes and here are the results:

frame size: 1518
Clock cycles: 144845
CPU Freq: 550 MHz
Cycles time: 263 us
Wireshark: 52 Mbits
-------------------------------
100 Mbits -> 121.44 us

Cycle time according to bandwith look correct but still I am loosing about a half bandwith so something is slowing me down.

You wrote:

With default GEL configure - hotmenu ARM_OPP100_Config()

{

GEL_TextOut("****  AM335x ALL PLL Config for OPP == OPP100 is in progress ......... \n","Output",1,1,1);

GetInputClockFrequency();

if(CLKIN==24)

{

  MPU_PLL_Config(  CLKIN, 23, 600, 1);

I am not sure if I undestand you correct. I am just running the device using target configuration and I didn't change the default GEL file:

Should I change it on: TMDXICE3359_v2_1A.gel? To be honest my board is rev 2.1 but till now nothing caught my attention using examples. This is console output during startup:

CortxA8: Output: ****  AM3359_ICE Initialization is in progress .......... 
CortxA8: Output: ****  AM335x ALL PLL Config for OPP == OPP100 is in progress ......... 
CortxA8: Output: Input Clock Read from SYSBOOT[15:14]:  24MHz
CortxA8: Output: ****  Going to Bypass... 
CortxA8: Output: ****  Bypassed, changing values... 
CortxA8: Output: ****  Locking ARM PLL
CortxA8: Output: ****  Core Bypassed
CortxA8: Output: ****  Now locking Core...
CortxA8: Output: ****  Core locked
CortxA8: Output: ****  DDR DPLL Bypassed
CortxA8: Output: ****  DDR DPLL Locked
CortxA8: Output: ****  PER DPLL Bypassed
CortxA8: Output: ****  PER DPLL Locked
CortxA8: Output: ****  DISP PLL Config is in progress .......... 
CortxA8: Output: ****  DISP PLL Config is DONE .......... 
CortxA8: Output: ****  AM335x ALL ADPLL Config for OPP == OPP100 is Done ......... 
CortxA8: Output: ****  AM335x DDR3 EMIF and PHY configuration is in progress... 
CortxA8: Output: EMIF PRCM is in progress ....... 
CortxA8: Output: EMIF PRCM Done 
CortxA8: Output: DDR PHY Configuration in progress 
CortxA8: Output: Waiting for VTP Ready ....... 
CortxA8: Output: VTP is Ready! 
CortxA8: Output: DDR PHY CMD0 Register configuration is in progress ....... 
CortxA8: Output: DDR PHY CMD1 Register configuration is in progress ....... 
CortxA8: Output: DDR PHY CMD2 Register configuration is in progress ....... 
CortxA8: Output: DDR PHY DATA0 Register configuration is in progress ....... 
CortxA8: Output: DDR PHY DATA1 Register configuration is in progress ....... 
CortxA8: Output: Setting IO control registers....... 
CortxA8: Output: EMIF Timing register configuration is in progress ....... 
CortxA8: Output: EMIF Timing register configuration is done ....... 
CortxA8: Output: PHY is READY!!
CortxA8: Output: DDR PHY Configuration done 
CortxA8: GEL Output: Turning on EDMA...  
CortxA8: GEL Output: EDMA is turned on...  
CortxA8: Output: ****  AM3359_ICE Initialization is Done ******************

Next - should I change something in GEL file if I want to increase clock or changing clock in BIOS setup is all I have to do?

BR,
Dawid.

--- EDIT ---

I checked throughput with 550 MHz, 600 Mhz and 800 MHz and every configuration looks very similar in timings (just like I wrote, about 144-145k cycles). So I think that delays are generated somewhere and I don't know where exactly.

0 Garrett Ding over 7 years ago in reply to Dawid Balcerzak

TI__Mastermind 43296 points

Dawid,

The GEL script by default configures the ARM core frequency to 600MHz, so accordingly the CPU clock frequency (Hz) should be set to 600000000; in the BIOS cfg. In addition to the OPP100, there are OPP120 and turbo configuration for CPU clock frequency but the VDD_MPU must also be set to 1.2V/1.26V, see ccs_base\emulation\boards\ice_am3359\gel\TMDXICE3359.gel.

If you enable DEBUG_TIMING_PRUSS in the project, what's the output look like?

Regards,
Garrett

0 Dawid Balcerzak over 7 years ago in reply to Garrett Ding

Expert 1365 points

Garrett,

when I enable DEBUG_TIMING_PRUSS in the project I can see lots of errors:

According to clock speed - I found ARM_Turbo_Config() in GEL, but I don't know where I should define VDD_MPU, I can't see it in GEL file. Where should I look for this parameter?

BR,
Dawid.

0 Garrett Ding over 7 years ago in reply to Dawid Balcerzak

TI__Mastermind 43296 points

Hi Dawid,

DEBUG_TIMING_PRUSS appears to be only applicable to __LINUX_USER_SPACE. And I think VDD_MPU is hardware dependent, you are not really able to modify the signal on the ICE board or re-define from GEL file.

The ICSS_EMAC example have both Tx/Rx enabled and looped back. Have you tried to comment out Tx and inject packet from external traffic generator to see if the performance is improved?

Regards,
Garrett

0 Dawid Balcerzak over 7 years ago in reply to Garrett Ding

Expert 1365 points

Hi Garrett,

I tried with my own Tx task. I commented out Tx tasks from example. Here is my code:

int32_t retvalTx;
Void taskSendPacket(UArg a0, UArg a1)
{

    ICSS_EmacTxArgument txArgs;
    txArgs.icssEmacHandle = ICSS_EMAC_testHandle;
    txArgs.lengthOfPacket = ETHERNET_FRAME_SIZE_1518;
    txArgs.portNumber = 1;
    txArgs.queuePriority = 3;
    txArgs.srcAddress = &dummyPkt[0];

  while(1) {
    //Send packet on PORT 1*. Size is known previously
    retvalTx = ICSS_EmacTxPacket(&txArgs, NULL);
  }
}

Maximum speed I achieved is 52 Mbps.

Such big delay is a reason why I asked about bare metal application with Ethernet funcionality.

0 Garrett Ding over 7 years ago in reply to Dawid Balcerzak

TI__Mastermind 43296 points

Hi Dawid,

Did you comment out "memcmp(&ICSS_EMAC_testTtsRecvPktPort1[0]..." while benchmarking the Rx throughput? I will try to get the benchmarking procedure/data from system test team...

Regards,
Garrett

0 Dawid Balcerzak over 7 years ago in reply to Garrett Ding

Expert 1365 points

Hi Garrett,

no, I didn't.

BR,
Dawid.

0 Garrett Ding over 7 years ago in reply to Dawid Balcerzak

TI__Mastermind 43296 points

Hi Dawid,

Do you see Rx tput improvement with memcmp() commented out? Also can you please point me the 'TI wiki sources' that lists ~90Mbps you referred to?

Regards,
Garrett

0 Dawid Balcerzak over 7 years ago in reply to Garrett Ding

Expert 1365 points

This is source:

Where I can find 'Rx tput improvement'?

BR,
Dawid.

0 Garrett Ding over 7 years ago in reply to Dawid Balcerzak

TI__Mastermind 43296 points

Hi Dawid,

The result shown in the wiki you referred to was collected from Processor SDK Linux and is likely from AM572x EVM. Though the PRU-ICSS firmware is compatible between Linux and RTOS, the host driver/application are not, which may explain the throughput discrepancy.

'Rx tput improvement' - I meant if you comment out memcmp() that would reduce the latency of DDR memory read and comparison, and may notice the throughput improvement.

Regards,
Garrett

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