AM4372: L2 cache configuration

Sh.Sasaki

Part Number: AM4372

Hi all,

Since the AM4372's L2 cache is enabled by default, setting of registers is not necessary when L2 cache is used.

Is this correct?

Looking at the following files in the pdk (TI-RTOS SDK) folder, when using the L2 cache, the code sets the PRCM_CM_PER_SPARE 0 _ CLKCTRL register.
However, since there is no entry in TRM for this register, we do not know whether this register setting is necessary to validate the L2 cache.
Is this register setting necessary?

C:\ti\pdk_am437x_1_0_9\packages\ti\starterware\soc\am43xx\am43xx_control.c

int32_t SOCL2SramConfig(uint32_t l2SramFlag)
{
uint32_t ctrlRegVal = 0;
int32_t status = S_PASS;

/* TODO: Check of correct clock input to L2SRAM - CONTROL_MPUSS_CTRL. */

if(L2_CONFIG_AS_SRAM ==l2SramFlag)
{
PL310Disable();
}

if((L2_CONFIG_AS_CACHE == l2SramFlag) || (L2_CONFIG_AS_SRAM ==l2SramFlag))
{
/* PRCM_CM_PER_SPARE0_CLKCTRL 0x4e8U
SOC_CM_PER_REG 0x44df8800U
L4LS_GCLK
PRCM_CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_GCLK_MASK */
/* TODO: Use PRCM module enable */
HW_WR_REG32((SOC_CM_PER_REG + PRCM_CM_PER_SPARE0_CLKCTRL),
PRCM_CM_PER_SPARE0_CLKCTRL_MODULEMODE_ENABLE);

while((HW_RD_REG32(SOC_CM_PER_REG + PRCM_CM_PER_SPARE0_CLKCTRL) &
PRCM_CM_PER_SPARE1_CLKCTRL_IDLEST_MASK) !=
PRCM_CM_PER_SPARE1_CLKCTRL_IDLEST_FUNC);

ctrlRegVal = HW_RD_REG32(SOC_CONTROL_MODULE_REG + CTRL_SEC_SPARE0);
ctrlRegVal = ((ctrlRegVal & ~CTRL_SEC_SPARE0_PIUSEL2SRAM_MASK) |
((l2SramFlag << CTRL_SEC_SPARE0_PIUSEL2SRAM_SHIFT) &
CTRL_SEC_SPARE0_PIUSEL2SRAM_MASK));

HW_WR_REG32(SOC_CONTROL_MODULE_REG + CTRL_SEC_SPARE0, ctrlRegVal);
}
else
{
status = E_INVALID_PARAM;
}
return status;
}

Best regards,

Sasaki

over 7 years ago

0 Biser Gatchev-XID over 7 years ago

TI__Guru**** 393215 points

The RTOS team have been notified. They will respond here.

0 lding over 7 years ago in reply to Biser Gatchev-XID

TI__Guru* 95265 points

Hi,

For AM437x, The L2 setting as cache or SRAM is controlled by CTRL_MPU_L2 Register (0x44e1_01e0) BIT 16. When SOC out of reset, this default setting is 256KB cache. This is the above code SOC_CONTROL_MODULE_REG + CTRL_SEC_SPARE0.

In the mentioned starterware code, PRCM_CM_PER_SPARE0_CLKCTRL 0x4e8U, I didn't find this register in AM437x technical reference manual, it is supposed to be in Table 6-191. CM_PER Registers. The code seems to enable the PRCM domain of CTRL_SEC_SPARE0. I think it is no harm to leave the undocumented code here.

Regards, Eric

0 Sh.Sasaki over 7 years ago in reply to lding

Guru 13625 points

Hi Eric-san,

Thank you for your support.
Is the PRCM domain of CTRL_SEC_SPARE0 enabled by default? Does not the user need to do this?

Best regards,
Sasaki

0 lding over 7 years ago in reply to Sh.Sasaki

TI__Guru* 95265 points

Hi,

I looked at this register 0x44df8ce8 using a JTAG when the AM437x board is powered on, the value is 0x0003_0000. That is 3h (R) = Module is disabled and cannot be accessed from bit 17:16.

The code:
HW_WR_REG32((SOC_CM_PER_REG + PRCM_CM_PER_SPARE0_CLKCTRL),
PRCM_CM_PER_SPARE0_CLKCTRL_MODULEMODE_ENABLE);

while((HW_RD_REG32(SOC_CM_PER_REG + PRCM_CM_PER_SPARE0_CLKCTRL) &
PRCM_CM_PER_SPARE1_CLKCTRL_IDLEST_MASK) !=
PRCM_CM_PER_SPARE1_CLKCTRL_IDLEST_FUNC);

checking bit 17:16 until it is 0: 0h (R) = Module is fully functional, including OCP.

So by default this CTRL_SEC_SPARE0 is disabled in PRCM, customer needs above code to enable it.

Regards, Eric

0 Sh.Sasaki over 7 years ago in reply to lding

Guru 13625 points

Hi,

Thank you for your support.
Do I need the above code to use L2cache?

Best regards,
Sasaki

0 lding over 7 years ago in reply to Sh.Sasaki

TI__Guru* 95265 points

Hi,

No. When SOC out of reset, this default setting is L2 used as 256KB cache.

Regards, Eric

0 Sh.Sasaki over 7 years ago in reply to lding

Guru 13625 points

Hi Eric-san,

Thank you very much for your reply.

I got it.

Best regards,

Sasaki

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AM4372: L2 cache configuration