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DM365_SPI interface

seol hee park
Prodigy 210 points

dear all,

i know that dm365 allows a programmable data length max.16bit for SPI interface..

but,  i hope configure it as below.

do you have a good idea?

pls, advise me.

i expect i can be of some help, i attached transfer function of my SPI_test source.

#define SPI_DEVICE_PATH  "/dev/spidev1.0"


#define BUF_SIZE 4
#define PRINTD printf

static uint8_t mode = SPI_MODE_2;
static uint8_t bits = 16;
static uint32_t speed = 700000;
static uint16_t delay = 0;
static uint16_t cs_change = 1;


static void TransferSpiDev(int spifd, int size, char* tx_buf, char* rx_buf)
{
 int ret;
    struct spi_ioc_transfer tr;

    tr.tx_buf = (unsigned long)tx_buf;
    tr.rx_buf = (unsigned long)rx_buf;
    tr.len = size;
    tr.delay_usecs = delay;
    tr.speed_hz = speed;
    tr.bits_per_word = bits;
    tr.cs_change = cs_change;

    ret = ioctl(spifd, SPI_IOC_MESSAGE(1), &tr);
    if (ret == 1){
        PRINTD("can't send spi message");
        return ;
    }
    PRINTD("Send/Recv %d Bytes Done\n", size);

}

  • 0
    Prodigy 80 points

    Hi,

    I have done something very similar on the DM6437 implementing read/write cycles on 32bit SPI transfers to communicate with a slave processor. The DM6437 supports 32bit transfers though. Not sure about the DM365.

    If you're communicating to a slave processor you might be able to change the comms protocol to work using 16bit transfers as supported by the DM365.

    If all fails perhaps you could "bit-bang" SPI by configuring your SPI pins as GPIO.

    Marcos

  • 0 in reply to Marcos Agra-Trillo
    TI__Genius 9490 points

    Soul Hee,

    I think you have 2 possible options.

    1) use the CSHOLD feature and hold the CS for every 2 16b word writes, and issue the consecutive writes/reads, however there will be small delay between the 2 16bit word writes and the clk will be held for that delay.

    2) you can use the MCBSP in SPI mode, and use the trick or code as Marcos did for DM6437, where he implemented read/write cycles on 32bit SPI transfers.

    regards,

    miguel