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HWI Context Switch latency

Shiri Ha
Prodigy 70 points
Other Parts Discussed in Thread: TMS320VC5509A

Hi,

I am working on TMS320VC5509A DSP, 200MHz, DSP Bios.

 I have a task which sometimes gets interrupted by HWI.

How many clock cycles would you expect the context switch to take? (from Task to HWI and back)

In my measurements I see that the context switch takes  7us , is it normal?

 

Thank you,

Shiri.

  • 0
    TI__Genius 13045 points

    Shiri,

    Are you using BIOS?  Your measurement seems high.  With 200MHz CPU speed you should get approximately 1400 instructions executed.  I don't have any numbers to share, but I wouldn't expect more than 10's of cycle for context save and restore.  How many cycles does your HWI take to execute?  That is user dependent. 

    Details on how the CPU manages interrupts is given in C55x CPU Reference Guide (http://www-s.ti.com/sc/techlit/spru371), sec 5.3.3.  The biggest items in interrupt latency are the pipeline flushes required for branching to and from the HWI.  Section 1.7 has details on the instruction pipeling.

    Regards.

  • 0 in reply to TommyG
    Prodigy 70 points

    That makes sence - I have an 'if' cmd in the task.

    You wrote 1400 instructions - that is exactly what I got !   1400* 5ns = 7us

    Is it ok then?

    You asked: ' How many cycles does your HWI take to execute? ' - do you want me to count from the disassembly?

     

    Thank you for the fast reply,

    Shiri.

  • 0 in reply to Shiri Ha
    TI__Genius 13045 points

    Shiri,

    Sorry, I wasn't clear enough before.  What I meant was that 7 usec is equivalent to about 1400 CPU cycles which seems too long for running a short HWI.  Context save and restore would take less than 100 cycles normally, I believe.  So remainder of time would be taken by your HWI.  That is the reason for asking how long it takes to run your HWI.  The 7 usec you are seeing seems too long for normal operation.

    Of course there are circumstances that can effect latency of HWI, that is why I pointed out the CPU Reference Guide which details how the HWI and instruction pipeline works.

    Regards.