Hello,
I am currently developing an XGE driver for my keystone K2K board and it is almost done but there is a remaining issue that I don't understand well.
Indeed, most of the time, there is an issue with serdes initialization because PCS-R Rx doesn't lock properly : the lock bit (30) of the PCSR_Rx_Status register (address 0x02f0060C) is not set.
Because of that, I can't receive any packet but I can however transmit them.
I checked the linux driver and saw that after the serdes initialization, the linux driver reset many times the PCS-R signal detection until the link is up by writing 1 then 0 in bit 2 of register lane_004 at address 0x0231e0204 (can be seen in linux driver at driver/phy/phy-keystone-serdes.c, function kserdes_wait_link_up).
On DSP, I use the serdes initialization from the example on the following file : pdk_k2hk_4_0_9/packages/ti/diag/serdes_diag/test/k2k/c66/bios/serdes_diag_test_init.c (I use CSL_SERDES_FUNCTIONAL_MODE instead of CSL_SERDES_DIAGNOSTIC_MODE for the operating mode of the serdes).
On this example, I didn't see the reset of PCS-R signal detection until link is up so I added it myself after the serdes initialization and saw that in most case, the link is finally up.
So here are my questions:
- Do the reset of signal detection after serdes initialization is really needed to make the Rx lock ? if yes, why ?
- Is there a cleaner way to make Rx lock than reset signal detection until link is up ? from my test, even with the several reset, the link is not always up and this fix seems to me a little dirty.
Also, I don't know where to report this but during my development, I found a few mistakes in CSL and documention so I will put them here in the hope they will be fixed in a next release:
- On the file pdk_k2hk_4_0_9\packages\ti\csl\src\ip\xge\V0\cslr_xge_cpsw.h, the RSVD1 field of the CSL_Xge_cpswRegs struct should be an array of 24 bytes instead of 20 bytes.
- On the 10 Gigabit Ethernet Switch Subsystem User Guide for KeyStone II Devices, there is some mistakes with the registers offset:
- On the summary of modules (table 3.2) There is a 4 bytes shift from register MAC_RX_PAUSE at offset 0x141C (should be 0x1418) to register MAC_Tx_Gap at offset 0x142C (should be 0x1428)
- On the 3.6 10Gb Ethernet switch section, table 3.44, there is a shift of 0x300 bytes from emac1 submodule at offset 0x100 (should be 0x400) to stats2 submodule at offset 0x700 (should be 0xA00)
For information, I use :
- the latest Processor SDK RTOS version 04_03_00_05
- a keystone 2 k2k board
- The MS_TI_RTM_BOC_REVD card for XGE
Thank you,
Julien