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AM3356: RMII timings issue

Peng Liu50174
Expert 1510 points
Part Number: AM3356

Hi,

I'm using AM3356 to connect to EMAC chip LAN8720A.

LAN8720 toggle its RXD, CRS_DV and RXER at the rising edge of its 50MHz clock output REFCLK, the Max Tco is 5ns. 

While AM3356 also latches the RXD, CRS_DV and RXER at the rising ege of REFCLK input according to Figure 7-11 in the datasheet, it requires setup of 4ns and hold of 2ns.

When connecting LAN8720 signals directly to AM3356 without addional timing adjustment component, the RXD, CRS_DV and RXER's  setup and hold time may not be met for AM3356, or may not have enought margin.

So is  there one configuration resister in AM3356 that I can set the processor to latch RXD, CRS_DV and RXER at the falling edge of the REFCLK to increase the setup time and hold time margin?

Thanks,

Peng,

  • 0
    TI__Guru**** 393215 points
    The factory team have been notified. They will respond here.
  • 0 in reply to Biser Gatchev-XID
    Expert 1510 points

    Hi,

    I added RC to the RXD,CRS_DV signals to have delay on these signals against REF_CLK. This can make the Tsu/Thold of RXD, CRS_DV meet AM335X requirement per datasheet Table 7-14.

    However adding RC will increase the rise/fall time of RXD, CRS_DV. For example the 10%~90% rise time of CRS_DV can reach to 17ns ( Vil to Vih :7ns). The captured waveform is shown below.

    Although the LAN works very well with this slow RXD, CRS_DV rise/fall time, we still have the conern.

    The question is since there is no requirment of the rise/fall time for RXD, CRS_DV in the datasheet, is this 17ns or 7ns any risk to the AM335X processor? If it is one risk, what is the rise/fall time limit for RXD, CRS_DV signals?

    Thanks,

    Peng,

  • 0 in reply to Peng Liu50174
    Expert 1510 points
    Hi,

    I saw in the datasheet table 7-5, the EMAC input signals rise/fall time is defined as 5ns maximum.
    is this 5ns is measued from 10% to 90% of the waveform, or from Vil to Vih?

    If the LAN interface works well with more than 5ns rise/fall time, then what is the potential risk or issue to the processor?

    Thanks,
  • 0 in reply to Peng Liu50174
    TI__Mastermind 27890 points
    Hello Peng,
    Sorry for the delay; I'm waiting to hear back from our Design team with an answer to your question regarding potential risk. My concern is that in increasing the Rt/Ft beyond the specified limits, that you may be stressing the IO cell due to the signal dwelling between VIH and VIL for a longer period of time. It may be next week before I can answer this question.

    As for your other question, the 1-5ns rise/fall time requirement for RMII IO's is defined by the RMII specification as between 0.8 and 2.0V.
  • 0 in reply to -DK-
    TI__Mastermind 27890 points
    Hi Peng,
    Feedback from the Design team is as follows:

    Excessive rise time can result in:
    - RX Timing degradation
    - Higher chances of noise coupling – essentially a weak driver has more chances of noise coupling than a strong driver
    - Reliability issues since the High/Low side driver will be ON for a longer duration. In most cases, could be out of spec of design if the rise/fall times are >> than characterized values.

    The recommendation is to correct your board layout to accommodate the timing requirements of the interface.