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DM6446 DDR2 Layout - CK to DQS timing - TDQSS requirement (re:SPRAAC5G)

Tiger Team4268
Intellectual 760 points

I am in the process of matching the DDR2 memory trace lengths and have a question about the relationship of the CK/ADDR_CTRL and the DQS/DQ group signals. I have used the SPRAAC5G application note as a guideline, but do not see any requirement between the CK clock and the DQS data strobe documented. Is there none?

There is a TDQSS timing relation requirement in the Micron and Samsung DDR2 datasheets:

"DQS rising edge to CK rising edge (Micron)" or "DQS latching rising transitions to associated clock edges (Samsung)"where the CK has to be matched to the DQS strobes by 0.25CK

Is this covered by the guideline presented in the SPRAAC5G application note?

  • 0
    Intellectual 760 points

    In thinking about this a little more, I suppose that this requirement  could be captured in the "X" and "Y offset" values in table #4 of the SPRAAC5G application note, but it is not obvious if it is.

    If the tCK is a nominal 3ns, then Tdqss would be 750ps or roughly 750/150 = 5inches which is obviously covered by any typical routing given the X, Y, Yoffset values in table 4 on page 6.

    So to answer my own question, this timing requirement is captured in the application note indirectly and there is no overt matching required of the CK/ADDR_CTRL and DSQ/DQ groups. (right?)

     

  • 0 in reply to Tiger Team4268
    TI__Mastermind 41665 points

    Tiger Team said:
    So to answer my own question, this timing requirement is captured in the application note indirectly and there is no overt matching required of the CK/ADDR_CTRL and DSQ/DQ groups. (right?)

    This is my understanding, any timing requirements are met by keeping within the guidelines of the application note, if you start making traces that are longer than the application note covers than you would have to take the additional timing requirements as you describe into consideration.