If only 32-bit data bus is used, must the remaining signal pins (DQS[8:4], /DQS[8:4], DQ[63:32], CB[7:0], DM[8:4]) in the data net class be left floating?
The following document describes "Unused DDR3 Pin Requirement", but does not seem to mention the remaining signal pins in the data net clas.
Hardware Design Guide for KeyStone Devices (Rev. C)
http://www.ti.com/lit/an/sprabi2c/sprabi2c.pdf
6.8.4 Unused DDR3 Pin Requirement (Page 74)
Best regards,
Daisuke
