Linux: DPLL internal PCIE 100MHz

user1897841

Tool/software: Linux

Hi，all

DRA75xx provides the 100MHz clock for PCIE。How to configure the register？Do you have reference code?Thanks for your recovery。

over 7 years ago

0 Shravan Karthik over 7 years ago

TI__Genius 14650 points

Hi,

The clocks for PCIe PHY are set in the function ti_pipe3_get_clk, in the file drivers/phy/phy-ti-pipe3.c.
Please note the that on DRA75x the frequency must be set to 100Mhz for proper PCIe operation (for more information refer to section 26.4.4.4.1.6 of the TRM -- link pasted below).

www.ti.com/.../sprui30e.pdf

Regards
Shravan

0 user1897841 over 7 years ago in reply to Shravan Karthik

Intellectual 420 points

Hi,

I've seen the file drivers/phy/phy-ti-pipe3.c.I found a lack of " .data = dpll_map_pcie" as follows:

static const struct of_device_id ti_pipe3_id_table[] = {
{
  .compatible = "ti,phy-usb3",
  .data = dpll_map_usb,
},
{
  .compatible = "ti,omap-usb3",
  .data = dpll_map_usb,
},
{
  .compatible = "ti,phy-pipe3-sata",
  .data = dpll_map_sata,
},
{
  .compatible = "ti,phy-pipe3-pcie",
},
{}
};

At the same time, it is found that the configuration of this structure "pipe3_dpll_params" is not consistent with the configuration of PCIe. Do you have a solution? Thanks.

0 Shravan Karthik over 7 years ago in reply to user1897841

TI__Genius 14650 points

Hi,

It is possible to use the clock-framework to configure the PCIe phy similar to that for USB and SATA, however this hasn't been implemented and instead is configured as part of PRCM, where the input clock (system-clock) is fixed.
Please note the output of the DPLL_PCIE_REF is expected to be 100Mhz, which is then fed as input to the APLL_PCIE, which then configures the lane frequency (refer section of the TRM provided in the previous post). So while its possible to have a structure similar to the one used for USB and SATA, the output will still have to be 100Mhz.

Regards
Shravan

0 user1897841 over 7 years ago in reply to Shravan Karthik

Intellectual 420 points

Dear Shravan,

Have anyone in your group configured PCIe 100MHz clk? Help us with the consultation,we are particularly anxious about the PCIe project.The boss asks for a quick solution.Please give us more help.Thanks very much.

Dahua Technology Co., Ltd

0 Shravan Karthik over 7 years ago in reply to user1897841

TI__Genius 14650 points

Hi,

I'm not sure I quite follow your question. The output of DPLL_PCIE_REF is 100Mhz and is set using the function ti_pipe3_get_clk in drivers/phy/phy-ti-pipe3.c, specifically in the call devm_clk_get(dev,"dpll_ref_m2"). You can confirm that the clock speed is 100Mhz by running the below command on the target:

omapconf show dpll

Search for the entry DPLL_PCIE_REF, the output is set to 100Mhz.

Regards
Shravan

0 user1897841 over 7 years ago in reply to Shravan Karthik

Intellectual 420 points

Hi,

omapconf show dpll, as follow.Please help see where there is a problem.Thanks.

0 Mariya Petkova over 7 years ago in reply to user1897841

TI__Expert 4885 points

Hi, user1897841,

As I see from your picture, the PCIE DPLL is configured properly. Its output clock is 100MHz. This output clock is supplied to the APLL to generate the required 2.5 or 1.25 GHz clock.

Pay attention that you should set a proper values in the following bits CM_CLKMODE_APLL_PCIE.REFSEL and CM_CLKMODE_APLL_PCIE.CLKDIV_BYPASS. The first one selects the reference clock for the APLL. The second one selects the output divider, i.e. whether the output APLL clock shall be 2.5Ghx or 1.25Ghz. For more information about these bits, please refer to 3.11.15 CM_CORE__CKGEN Registers section in the same document Shravant had given a link above.

Regards,
Mariya

0 user1897841 over 7 years ago in reply to Mariya Petkova

Intellectual 420 points

Dear Mariya,

After CTRL_CORE_SMA_SW_6[17:16]=0x01 and CM_CLKMODE_APLL_PCIE[7]=0, Why can't I measure the clock signal 100MHz from pin LJCB_CLKN and LJCB_CLKP？

0 Stanislav Stilyanov over 7 years ago in reply to user1897841

TI__Mastermind 19040 points

Hi,

I would like to recommend TRM section 26.4.5 PCIePHY Subsystem Low-Level Programming Model.

It was validated and works fine for PCIe PHY initialization and clocking.

Regards,

Stan

0 user1897841 over 7 years ago in reply to Stanislav Stilyanov

Intellectual 420 points

Dear Stan

Do you have the related configuration code? Thanks for your help.

0 Shravan Karthik over 7 years ago in reply to user1897841

TI__Genius 14650 points

Hi,

If you want to use DPLL_PCIE_REF as input clock to APLL it is configured using the below call in the function ti_pipe3_get_clk in the file drivers/phy/phy-ti-pipe3.c (this is the default configuration)

clk = devm_clk_get(dev, "dpll_ref_m2");
if (IS_ERR(clk)) {
dev_err(dev, "unable to get dpll ref m2 clk\n");
return PTR_ERR(clk);
}
clk_set_rate(clk, 100000000);

If you want to set APLL input clock as ASPCIE then apply the below patch on kernel. The exact details of the registers set is available in the TRM (link provided in previous posts).

Regards

Shravan

Fullscreen 0001-phy-pcie-Set-APLL-reference-input-clock-as-ACSPCIE.patch.txt Download

From 5a16e6f5223b06e076c5d97f57b626721486a03a Mon Sep 17 00:00:00 2001
From: Shravan Karthik <shravan.karthik@ti.com>
Date: Fri, 8 Jun 2018 15:51:05 +0530
Subject: [PATCH] phy: pcie: Set APLL reference input clock as ACSPCIE

Set mux configurationt to enable ACSPCIE as APLL input clock
Also set ASCPCIe in RX Mode and disable dpll_ref_m2 clock
---
 drivers/phy/phy-ti-pipe3.c | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index bf46844..f3f75f1 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -410,12 +410,14 @@ static int ti_pipe3_get_clk(struct ti_pipe3 *phy)
 		}
 		clk_set_rate(clk, 1500000000);
 
+/*
 		clk = devm_clk_get(dev, "dpll_ref_m2");
 		if (IS_ERR(clk)) {
 			dev_err(dev, "unable to get dpll ref m2 clk\n");
 			return PTR_ERR(clk);
 		}
 		clk_set_rate(clk, 100000000);
+*/
 
 		clk = devm_clk_get(dev, "phy-div");
 		if (IS_ERR(clk)) {
@@ -423,7 +425,6 @@ static int ti_pipe3_get_clk(struct ti_pipe3 *phy)
 			return PTR_ERR(clk);
 		}
 		clk_set_rate(clk, 100000000);
-
 		phy->div_clk = devm_clk_get(dev, "div-clk");
 		if (IS_ERR(phy->div_clk)) {
 			dev_err(dev, "unable to get div-clk\n");
@@ -551,6 +552,19 @@ static int ti_pipe3_probe(struct platform_device *pdev)
 	struct device_node *node = pdev->dev.of_node;
 	struct device *dev = &pdev->dev;
 	int ret;
+	uint32_t readval;
+
+	void __iomem *txrxregs = ioremap(0x4a003c14, 4);
+	readval = (uint32_t) readl(txrxregs);
+	readval |= 0x20000;
+	writel(readval,txrxregs);
+	iounmap(txrxregs);
+
+	void __iomem *muxregs = ioremap(0x4a00821c, 4);
+	readval = (uint32_t) readl(muxregs);
+	readval |= 0x180;
+	writel(readval,muxregs);
+	iounmap(muxregs);
 
 	phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
 	if (!phy)
-- 
2.7.4

0 user1897841 over 7 years ago in reply to Shravan Karthik

Intellectual 420 points

Hi Shravan，

Can the address of (0x4a003c14 and 0x4a00821c) be mapped directly? Direct mapping leads to the kernel halt. Is there another function to be opened to guarantee address mapping ? Thanks.

0 Shravan Karthik over 7 years ago in reply to user1897841

TI__Genius 14650 points

Hi,

The patch provided has been tested and works fine, thus these addresses can be mapped directly. A condition check ensuring txrxregs and muxregs are not NULL can be used to guarantee address mapping.

The thread has been marked resolved, if you have any further queries, please initiate a new thread, we will support you.

Regards

Shravan

Processors

Processors forum

Linux: DPLL internal PCIE 100MHz