Linux/AM5728: OCMC3 for data sharing between ARM and DSP

Jimit Patel

Part Number: AM5728

Tool/software: Linux

I am working with AM5728 EVM. I running Linux on A15 and RTOS on DSP and M4 cores.I am using CMEM buffer pool to currently stream audio to the DSP. This buffer pool is currently allocated on the DDR and it works with it. Now I am trying to use L3 shared memory (OCMC3) for audio streaming. I haven't modified the am57xx-evm-cmem.dtsi as it already has entry for cmem_block_1 with ocmc3.

I am trying to allocate buffer on the Linux using this -

CMEM_AllocParams cmemParams;
cmemParams.type = CMEM_HEAP;
cmemParams.flags = CMEM_NONCACHED;

// Shared mem between A15 and DSP using cmem_block_mem_1_ocmc3
void * shared_mem = CMEM_alloc2(1, 0x100000, &cmemParams);

The CMEM_alloc2() call succeeds, but when I used this shared_mem for streaming audio, it seems that the audio data gets cached. Am I using correct CMEM_AllocParams or what am I missing?

Regards,

Jimit

over 7 years ago

0 Rex Chang over 7 years ago

TI__Guru 50170 points

Hi,Jimit,

Where do you see the data gets cached, on the ARM or DSP side? If on the DSP side, is it configured as non-cached?

Rex

0 Jimit Patel over 7 years ago in reply to Rex Chang

Intellectual 570 points

Hi Rex,

I see the data getting cached on the DSP. I am setting CMEM flag to CMEM_NONCACHED on the A15/Linux; on the DSP I am using the Resource_physToVirt() to access the region. Other then adding entry to the resource table, I am not doing any other configuration on DSP. How to configure it as non-cached on the DSP?

-Jimit

0 Sahin Okur over 7 years ago in reply to Jimit Patel

TI__Mastermind 27355 points

Hi Jimit,

For L3 memory, cache would need to be explicitly enabled by setting the corresponding MAR bits. This is usually done in the DSP's cfg file.

The platform file will define the amount of L1 and L2 used for cache. For example, the evmAM572x platform file has the following configuration:

/*
     *  ======== l1PMode ========
     *  Define the amount of L1P RAM used for L1 Program Cache.
     *
     *  Check the device documentation for valid values.
     */
    config String l1PMode = "32k";

    /*
     *  ======== l1DMode ========
     *  Define the amount of L1D RAM used for L1 Data Cache.
     *
     *  Check the device documentation for valid values.
     */
    config String l1DMode = "32k";

    /*
     *  ======== l2Mode ========
     *  Define the amount of L2 RAM used for L2 Cache.
     *
     *  Check the device documentation for valid values.
     */
    config String l2Mode = "0k";

L1D and L1P have cache enabled and L2 has cache disabled. Since L1D and L1P have cache enabled there will be some caching of data.

The platform file for your platform can be found under \bios_6_52_00_12\packages\ti\platforms\

I hope this helps.

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Linux/AM5728: OCMC3 for data sharing between ARM and DSP