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RTOS/AM3358: NAND bootloader

Expert 2730 points
Part Number: AM3358


Tool/software: TI-RTOS

I have problem with NAND bootloader. I'm debugging the bootloader project and the bootloader always stucks in DMTIMER_WAIT_FOR_WRITE macro. The project itself was missing (I guess) from the main function: 

/** \brief Global variable to instantiate the timer for providing a delay. */
timeUtilsObj_t freeRunTimer = {7U, TIME_CLOCK_SEL_24MHZ_EXT_CRY_OSC, TRUE, 0U};

/* Initialize the timer to make use of the delay functionality */ TIMEUtilsInit(&freeRunTimer, 0U);

because NAND libraries will use delay function. But then the code hangs in 

void DMTIMERSetCounterVal(uint32_t baseAddr, uint32_t counter)
{
    /* Wait for previous write to complete */
    DMTIMER_WAIT_FOR_WRITE(baseAddr,DMTIMER_POSTED_WRITE_STS_TCRR );

    /* Set the counter value */
    HW_WR_REG32((baseAddr + DMTIMER_TCRR), counter);
}

If I don't initialize the timer then it will hang also on DMTIMER_WAIT_FOR_WRITE(baseAddr, DMTIMER_POSTED_WRITE_STS_TCRR); 

int32_t NandLibWaitPinStatus(nandLibInfo_t *pNandLibInfo, uint32_t timeout)
{
    uint32_t status = NAND_LIB_PASS;
    uint32_t waitPinStatus = 0U;
    uint32_t chipSel = pNandLibInfo->nandLibCtrlInfo.chipSel;

    /*
    ** This function is called immediatly after issuing commands
    ** to the NAND flash. Since the NAND flash takes sometime to
    ** pull the R/B line low,it would be safe to introduce a delay
    ** before checking the ready/busy status.
    */
    NandLibDelay(1U);

    ==> 
uint32_t DMTIMERGetCounterVal(uint32_t baseAddr)
{
    /* Wait for previous write to complete */
    DMTIMER_WAIT_FOR_WRITE(baseAddr, DMTIMER_POSTED_WRITE_STS_TCRR);

    /* Read the counter value from TCRR */
    return (HW_RD_REG32(baseAddr + DMTIMER_TCRR));
}

Anything else I need to initialize to get the NAND bootloader to work?

JHi

  • The RTOS team have been notified. They will respond here.
  • Ok I solved the first problem. Had to add

    ifeq ($(BOOTMODE), nand)
    BUILDCFG_MOD_GPMC = 1
    BUILDCFG_MOD_DMTIMER = 1
    endif # ifeq ($(BOOTMODE), nand)

    to build_config.mk and now it goes past the DMTIMER_WAIT_FOR_WRITE macro.

    The next problem is a boot loop. I flashed my app software to NAND to offset 0x80000. If I start the bootloader with debugger from CCS the bootloader loads the app from NAND to RAM and start to execute is as it should, everything works. But if I flash the bootloader to NAND (offset 0x0) it remains in a boot loop:

    StarterWare Boot Loader
    BOARDInit status [0x0]
     SoC                   : [AM335X]
     Core                  : [A8]
     Board Detected        : [GPEVM]
     Base Board Revision   : [1.5]
     Daughter Card Revision: [UNKNOWN]
    NAND flash is connected to GPMC on this board
    
    **** Nand Device Info ****
    Manufacturer Id is 2c
    Device Id is       da
    Page size is       2048 bytes
    Block Size is      131072 bytes
    Pages per Block is 64
    *************************
    
    Reading Image From NAND
    Copying Header of the application image
    Copying image from flash to DDR
    

    I have no idea how to debug this. I can't even connect my debugger because it resets the controller all the time. I have to flash the NAND with linux MLO to get a connection with debugger. What could cause this? I have changed the board files to match my GEL file so it "shouldn't" be a clock problem but what else could it be?

    JHi

  • The boot loop is caused by the watchdog I guess, because the reset line goes low and it comes every two seconds. BUT the watchdog should be disabled with SBLPlatformConfig()

    HW_WR_REG32((SOC_WDT_1_REGS + WDT_WSPR) , 0xAAAAU);
        while(HW_RD_REG32(SOC_WDT_1_REGS + WDT_WWPS) != 0x00U);
    
        HW_WR_REG32((SOC_WDT_1_REGS + WDT_WSPR) , 0x5555U);
        while(HW_RD_REG32(SOC_WDT_1_REGS + WDT_WWPS) != 0x00U);
    

    But I can't check the watchdog registers when I'm booting from NAND because I can't connect with my debugger as long as watchdog or any other source is giving resets.

    Edit:

    just checked the reset line with oscilloscope: Reset pulses comes every 1.6s and are 180ms low. I printed out the WDT_WSPR register and it shows 0x5555 before and after SBLPlatformConfig(). Any ideas what could cause the reset? If I program the linux MLO, I won't get any reset pulses. Also if running with debugger, I do not get any reset pulses.

  • A little bit more information. I printed out the reason for reboot (PRM_RSTST Register) and it shows 0x21 (I do not clear the bits) -> EXTERNAL_WARM_RST. If it really is external reset what could cause it only to trigger when I'm really booting from NAND and not if I launch the bootloader with debugger or MLO?
  • Solved the issue. In my controller module is also a external watchdog chip. I had to set one pin to correct state so that the watchdog is deactivated.