AM4378: DDR3 layout constraints

Brandon08

Part Number: AM4378

Team, do we specify DDR3 layout guidelines for AM437x? Specifically I am looking to understand if we have length restrictions between the DQS signals and clock signals. Do we have any reference collateral specific to this? I found a wiki related to DDR2 only. Thank you in advance!

over 8 years ago

0 Biser Gatchev-XID over 8 years ago

TI__Guru**** 393215 points

See section 5.13.8.2.1 in the AM437x Datasheet Rev. D.

0 Brandon08 over 8 years ago in reply to Biser Gatchev-XID

TI__Mastermind 24520 points

Biser, thanks. After reading the app note and referring to section 5.13.8.2.1.6.2 the associated table likely has my answer for length limits for DQS. The previous section discusses the clock & address line. We see in the datasheet there are length restrictions specified between DQ & DQS. There are also limitations between address control & clock signals. I do not see any rule given for clock and DQS signals, so it is my understanding no such rule exists. Do you agree?

0 Biser Gatchev-XID over 8 years ago in reply to Brandon08

TI__Guru**** 393215 points

Yes, this is correct.

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AM4378: DDR3 layout constraints