TMS320C6748: USB 2.0 PCB layout

Kurt Jensen

Part Number: TMS320C6748

http://processors.wiki.ti.com/index.php/OMAP-L138_Hardware_Design_Guide

Note: TI provides PCB layout specifications in the device datasheets for the following interfaces, eliminating the need to perform electrical analysis:
DDR
SATA
USB

Where might one find these "PCB layout specifications in the device datasheets"? (hint, NOT in the peripheral user guide...)

P.S. please be gentle with terminology and questions...I'm the firmware guy doing some side research...

over 7 years ago

0 Cvetolin Shulev-XID over 7 years ago

TI__Guru 65405 points

The team is notified. They will post their feedback directly here.

BR
Tsvetolin Shulev

0 Yordan Kovachev over 7 years ago

TI__Guru**** 161600 points

Hi Kurt,

See the following sections:
For DDR see Section 6.11.3.3 PCB Stackup through Section 6.11.3.12 DDR2/mDDR Boundary Scan Limitation
For SATA see Section 6.14.2.3 PCB Stackup Specifications through Section 6.14.3 SATA Unused Signal Configuration
For USB: Section 6.20.1 USB0 [USB2.0] Electrical Data/Timing.

Best Regards,
Yordan

0 Kurt Jensen over 7 years ago in reply to Yordan Kovachev

Genius 5040 points

Hi Yourdan,

Thanks for the references.

But...what document are these in...?

Kurt

0 Yordan Kovachev over 7 years ago in reply to Kurt Jensen

TI__Guru**** 161600 points

Hi Kurt,

Sorry, here is a link to the datasheet:
www.ti.com/.../tms320c6748.pdf

Best Regards,
Yordan

0 Kurt Jensen over 7 years ago in reply to Kurt Jensen

Genius 5040 points

OK. Found the sections in sprs590g.

Section 6.20.1 is basically timing data and timing diagram. Seems a little sparse on "PCB layout specifications". How could 6.20.1 possibly provide enough information to eliminate "the need to perform electrical analysis"?

0 Mark M over 7 years ago in reply to Kurt Jensen

TI__Mastermind 30280 points

Hi Kurt,

Refer to these resources for USB2.0 routing guidelines and high speed routing in general.

TMS320C674x/OMAP-L1x USB Compliance Checklist - http://www.ti.com/lit/an/sprab17/sprab17.pdf

High-Speed Interface Layout Guidelines - http://www.ti.com/lit/an/spraar7g/spraar7g.pdf
- Several recommendations for USB2.0
- Figure 13. USB2 Differential Signal Spacing (mils)

High Speed PCB Layout Techniques - http://www.ti.com/lit/ml/slyp173/slyp173.pdf

[edit] - general rules:

Plan to route USB differential pair signals first, on top layer if possible
Avoid stubs, differential pair length mismatch or impedance mismatch
Avoid any discrete components in DP/DM trace (except USB.org approved ESD components)

Hope this helps,
Mark

0 Kurt Jensen over 7 years ago in reply to Mark M

Genius 5040 points

Thanks Mark, One of those links is new.

In sprs590g, section 6.20.1, Table 6-91, No. 10, Z DRV - what is this Z DRV? and Z INP?

0 Mark M over 7 years ago in reply to Kurt Jensen

TI__Mastermind 30280 points

Hi Kurt,

Z DRV is the output impedance (single ended), 45 ohms nominally. Differential impedance (between complementary DP and DM traces) is double, 90 ohms nominally. These are useful when you specify the trace impedances for the PCB fab house. If you match the trace impedance with the output impedance, then signal reflections at the pin to trace junction are minimized. Signal distortions are minimized also.
Trace impedance can be calculated with online tools like this one: www.eeweb.com/.../edge-coupled-microstrip-impedance
But PCB houses will run their own calculations and tweak trace separation and widths.

Z INP is the input impedance of the input. High input impedance (orders of magnitude higher than source impedance) prevents any voltage divider effect on the input signal so that the maximum voltage swing propagates into the input with minimal current draw.

Hope this helps,
Mark

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TMS320C6748: USB 2.0 PCB layout