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reading and writing SRAM from CCS v3.3 using emulator XDS510USB Plus

I tried downloading my linked code for the first time got a data verification error at a location in my off chip SRAM. I then used my CCS memory

viewer and found that I could not write to the first location (0x600000 word address). It did not give me an error but it stored the value for the next

location in the first location. This is repeatable for every other location. Has anyone seen this type of problem or have any suggestions on how

to fix the problem?

Thanks

Barry

 

  • Do you have a GEL file set up to configure your EMIF registers? Is it possible that the bus is configured as 8-bit instead of 16-bit, or something of that nature? Can you provide a little more details regarding the EMIF->SRAM connection, as well as what type of SRAM you are using?

    Also, for clarification, if you write 0x1234 and 0x5678 to sequential memory does it show up as 34 00 78 00 ... or as something else?

  • Tim

    I am using a GEL file that TI supplied me. It is probably a generic one that I have not done anything to. I will look at the GEL file and documentation

    and get back with you.

    Thanks

    Barry Turner

  • Tim

    The following are the only two lines in the C5505.gel file I found related to the external memory I am trying to read/write to.

    GEL_MapAdd(0xC00000,0,0x200000,1,1);    /* External-Async */

    GEL_MapAdd(0x600000,1,0x100000,1,1);    /* External-Async */

    The memory is a 2 megabyte Cypruss chip model number CY62167EV18. I am using the memory option under view in the tool bar for CCS V3.3. When I write a value to the first word in the memory the value for the second word is stored instead of the value I enetered. I can correctly change the value for the second word without it effecting the value in the first word. This repeats for every other word. I cannot correctly change the value for words 1,3,5...etc.

    Thanks

    Barry

     

  • Hi Barry,

    Are you configuring the EMIF for SRAM in your code or you are using GEL file to configure EMIF. Since you are loading your code to SRAM I guess you will use GEL for configuring the EMIF. In that case make sure that SRAM initialization function(SRAM_INIT or something like that) in the GEL file is being called. You can invoke the SRAM/EMIF initialization function in the GEL file using the CCS GEL menu. Otherwise you can add the SRAM/EMIF init function call in OnTargetConnect() in the GEL file so that your EMIF will be configured during the target connection.

    Pratap.

     

     

  • Hi Pratap,

    I first tried to download my code using CCS. I got a memory verification error. I then decide to try to read and write into my off chip SRAM which is located at 0x600000 (word address). I could not write properly to every other location starting with the first one.

     

    I looked at the GEL menu in CCS and found that it had a SDRAM initialization but not one for SRAM. I assume this means I have to add an EMIF call to the GEL file to setup the interface to the specific SRAM I am using before I can read and write to. Is this correct?

     

  • Barry,

    If the EMIF registers for the CE space on which your SRAM is located are not configured correctly then there is no telling how the SRAM will react. As you implied you will need to create a small routine in the GEL file to configure the EMIF for your SRAM (initSram() or something like that).

    Let me know if you have questions about how to do this. It is fairly similar to coding in C, and you should be able to model if off something like the SDRAM initialization function.

  • menuitem "SDRAM_Configuration";

    hotmenu SDRAM_INIT() {

        *(short *)RESET_CONTRL@IO = 0x0002;

        *(short *)SDR_TIMING0@IO = 0x5810;

        *(short *)SDR_TIMING1@IO = 0x4221;

        *(short *)SDR_CONFIG0@IO = 0x4520;

        *(short *)SDR_CONFIG1@IO = 0x0031;

        GEL_TextOut("SDRAM Initilization Complete.\n");

    }

     

    Tim

    I can follow the above CCS generated code easy enough. I will have to determine where the control registers for the specific SRAM I am using are located in the I/O space and what values to store in the registers for the memory chip. I am not sure what the RESET_CONTROL does. The address represented by RESET_CONTROL is not near the other register addresses. Where can I find the information defining this?

    THANKS

    Barry Turner

  • Hi Baryy,

    RESER_CONTROL is Peripheral Reset Control Register. In SDRAM_INIT it is configured to reset the EMIF. Same configuration holds good for SRAM also. You can find the details of this register in DSP system user guide.

    You have to configure EMIF 'Asynchronous Wait Cycle Configuration Registers' and 'Asynchronous CSn Configuration Registers' for initializing the SARAM

    Pratap. 

  • Pretap,

    I had found the definition of all the registers and will try the initialization as you suggest on Monday.

    Thanks

    Barry

     

     

  • Pratap

    I am still having problems accessing my off chip SRAM (location 0x600000 word address – 2 megabyte).I have created a routine in my  GEL file that initializes the AWCCR1, AWCCR2, ACS3CR1, and the ACS3CR2 registers. I placed the call to it in the function OnTargetConnect in the GEL file. I see the SRAM message when I connect to the target. When I write 0x1234 to the first, third, etc..  locations the value 0x3434 is stored there. When I write 0x5678 to the second, fourth, etc…  locations the value 0x78 is store there.

     

    The code I wrote is as follows:

     

    #define SRAM_Async_Wait_Reg_1         0x1004

    #define SRAM_Async_Wait_Reg_2         0x1005

    #define SRAM_Async_CS3_Reg_1           0x1014

    #define SRAM_Async_CS3_Reg_2           0x1015

     

    menuitem "SRAM_Configuration";

    hotmenu SRAM_INIT() {

        *(short *)RESET_CONTRL@IO = 0x0002;

        *(short *)SRAM_Async_Wait_Reg_1@IO = 0x0080;

        *(short *)SRAM_Async_Wait_Reg_2@IO = 0x4030;

        *(short *)SRAM_Async_CS3_Reg_1@IO = 0x4520;

        *(short *)SRAM_Async_CS3_Reg_2@IO = 0x0031;

        GEL_TextOut("SRAM Initilization Complete.\n");

    }

     

    I put the call to SRAM_INIT in OnTargetConnect so I could see the message in the CCS box. I do not know much about the interface to SRAM and have no one here that does. Several of the values placed in the registers were arbitrarily picked around the midpoint of the range for the entry. I would appreciate any suggestions.

     

    Thanks

    Barry

     

  • Hi Barry,

    Try with the configuration *(short *)SRAM_Async_CS3_Reg_1@IO = 0x4521;

    Pratap.

  • Pratap

    It now consistently repeats the first byte in the second byte for each word I write in. If I write 0x1234 into a location 0x1212 will be displayed. There must be one more setting I have missed.

    Thanks

    Barry

     

  • Barry,

    Can you check the value at IO address 0x1c33. It should be set to '0' for 16bit EMIF access.

    Pratap.

  • Pretap

    I could not find a way to look at the registers through CCS V3.3. Can you tell me how to do this?

    Thanks

    Barry

     

  • Barry,

    Click on the CCS menu 'View' and select 'Memory'. A memory window will be opened on the right side of the CCS. At the bottom of the memory window In the second drop down menu select 'IO' and enter 0x1c33 in the filed that shows 'Enter An Address'.

    Pratap.  

  • Pratap

    The value stored there is 0x0002. I read that on reset the EMIF should be set to 16 bit. I am trying to find what the value stored there (0x0002) means.

    Thanks

    Barry

  • Pretap

    I restarted my CCS and manually went and changed the value at location 0x1c33 to 0. I can now read/write to my word addresses correctly. I just need to find out what is changing the ESCR (0x1c33) to 0x0002 everytime I connect to the target.

    Thanks

    Barry

     

  • Barry,

    You add setting the ESCR to 0x0 in your SRAM init function. In case you feel there will be some other modules depending on this configuration you can enable the word mode access while using the SRAM and set it back to byte mode once you finish the SRAM access.

    Pratap