DDR2 INTERFACE

The DDR interface on the DM6437 as well as many of our DDR using devices is not specified deeply in the datasheet, the reason being that the strategy for deployment of DDR interfaces in TI processors is to follow a specifically defined DDR reference design layout as opposed to provide specifications and have developers run simulations and make custom layouts for each new board. This being said, the DDR_CLK signal rise time is not defined by our specifications. For implementing your DDR2 layout with the DM6437 you should follow the guidelines in the Implementing DDR2 PCB Layout on the TMS320DM643x DSP application note, if the rules in this document are followed your DDR2 interface is sure to function properly, thus additional timing specifications should not be required and TI avoids giving them out.

Can I ask why you care?  If you follow the layout recommendations, use a standards compliant device, and perform VTP calibration at wakeup, you don't need to do timing analysis.

Well, I was thinking that the timming design will be different depending on which is the dielectric you are using to build your pcb. I mean, the delay will be different if you use a material with er= 4 or 4.3 or 4.5. isn't it?

So, is this document above a worst case analysis?

As I have seen several designs go through following the same DDR layout methodology with success without the dielectric coming up, I do believe the document covers a worst case analysis. Are you trying to make a DDR design that does not fit into the layout application note guidelines?