Linux/AM4372: I2C timings

The factory team have been notified. They will respond here.

Yimin,

What is your pullup strength on the I2C bus?

Which specific processor balls are you using for this I2C?

Can you specify the timing for both the case when AM437x is driving the I2C bus (e.g. while it outputs the slave address) as well as the timing observed when the slave device is controlling the data line (e.g. during master receive)?

Are you seeing this timing on both the SCL and SDA lines?

Thanks,
Brad

Hi SIr 

1.I2C Bus Pullup Resistor is 2.2k.

  The signal we tested is AM4376 I2C0 connected with PMIC. It is pulled up to VCC_3P3V ,which is provided by PMIC DCDC4.

2.  The photo was captured when system power on then am4376 was communicating with PMIC. And  AM4376 is driving the I2C bus.

3.  Yes, SCL and SDA falling time is almost same.

BR

Yimin

Yimin,

Thanks for the follow-up info. I'm consulting with some colleagues regarding your observed behavior. I hope to have some follow-up info for you soon. Thanks for your patience.

On a related note, are you seeing any resulting issues from the fast time, or were you just checking the general timing characteristics?

Best regards,
Brad

Hi Sir

we refer to below document about I2C Bus Pullup Resistor Calculation

     

It indicated that the pull up res impact on the rising time. But it seems unhelpful to the I2C falling time.

Refer to below pic, the rising time pass, but the falling time is only about 2.8ns.Can you help to confirm how to adjust falling time of I2C?

BR

Yimin

Yimin,

I'm sorry for the delay in responding to this issue.  The person with whom I needed to discuss the issue was out at the end of last week.  I hope to have a response to you today or tomorrow.

Brad

Hi Yimin,

The AM437x I2C min rise/fall timing for fast-mode does not match the I2C standard’s min rise/fall value of 20+0.1Cb ns. This is because the I2C was implemented using a standard LVCMOS I/O (rather than an open-drain I/O) on AM437x.

We will address this in the next AM437x documentation release.

Regards,
Melissa

Hi Sir

thanks for your reply.

The AM437x I2C min rise/fall timing for fast-mode does not match the I2C standard’s min rise/fall value of 20+0.1Cb ns. 

Could you advise what is the right min rise/fall we should follow for  AM437x I2C min rise/fall timing in fast-mode? 

And what content you will update in next document release ?

BR
Yimin

Hi Sir

BTW, do you have schedule about next AM437x documentation release ?

BR
Yimin

Hi SIr

Do you have any update for our questions ?

BR
Yimin

Hi Sir

do you have schedule about next AM437x documentation release ?

BR
Yimin

Part Number: AM4372

Tool/software: Linux

Hi Sir

we got the information as below 

The AM437x I2C min rise/fall timing for fast-mode does not match the I2C standard’s min rise/fall value of 20+0.1Cb ns. This is because the I2C was implemented using a standard LVCMOS I/O (rather than an open-drain I/O) on AM437x. 

We will address this in the next AM437x documentation release.

Does TI have any schedule to offer next AM437x documentation release?

BR

Yimin

Part Number: AM4372

Tool/software: Linux

Hi SIr

we got the reply from TI as below 

e2e.ti.com/.../2581949

The AM437x I2C min rise/fall timing for fast-mode does not match the I2C standard’s min rise/fall value of 20+0.1Cb ns.

This is because the I2C was implemented using a standard LVCMOS I/O (rather than an open-drain I/O) on AM437x.

We will address this in the next AM437x documentation release.

1.  Could you advise what is the right min rise/fall we should follow for  AM437x I2C min rise/fall timing in fast-mode? 

2.  Do you have the schedule about next AM437x documentation release?

thanks 

BR

Yimin

 

Hi Yimin,

I apologize for the delay. Below is an update to your questions.

1. The right value is that there is no min rise/fall time associated with the I2C fast-mode.
2. Our current plan is to publish this as an advisory in the device silicon errata. The release date has not yet been set, but I should know more in the next ~2 weeks.

Regards,
Melissa

Part Number: AM4372

Tool/software: Linux

Hi Sir 

Based on the last reply in following link 

     e2e.ti.com/.../2635885

1. The right value is that there is no min rise/fall time associated with the I2C fast-mode.
2. Our current plan is to publish this as an advisory in the device silicon errata. The release date has not yet been set, but I should know more in the next ~2 weeks.

Do you have any update about item2 ? when to release errata date for i2c issue 

BR

Yimin