problems of EDMA3 multiple channel transfering
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After I config my EDMA3 with following codes, the multiple channel transfering does't work well. It just transfers channel 0 data correctly. Do I miss some key configurations or the EDMA3 cannot work in this way?
Thanks!
code:
for( i = 0; i < 3; i++ )
{
tcc[i] = EDMA3_DRV_TCC_ANY;
chId[i] = EDMA3_DRV_DMA_CHANNEL_ANY;
if ( EDMA3_DRV_requestChannel ( hEdma, &chId[i], &tcc[i],
(EDMA3_RM_EventQueue)0,
callback, &myCbData[i] )!= EDMA3_DRV_SOK )
{
fail = -2;
return fail;
}
}
myCbData[0].numTrs = 576;
myCbData[0].numTrCnt = 0;
EDMA3_DRV_setSrcParams( hEdma, chId[0], (capYbuffer + 1),
EDMA3_DRV_ADDR_MODE_INCR,
EDMA3_DRV_W8BIT );
EDMA3_DRV_setDestParams ( hEdma, chId[0], (storeYbuffer1),
EDMA3_DRV_ADDR_MODE_INCR,
EDMA3_DRV_W8BIT );
EDMA3_DRV_setSrcIndex ( hEdma, chId[0], 2, 1440 );
EDMA3_DRV_setDestIndex ( hEdma, chId[0], 1, 784 );
EDMA3_DRV_setTransferParams ( hEdma, chId[0], 1, 720, 576, 720, EDMA3_DRV_SYNC_AB );
EDMA3_DRV_setOptField ( hEdma, chId[0], EDMA3_DRV_OPT_FIELD_TCINTEN, 1u );
EDMA3_DRV_setOptField ( hEdma, chId[0], EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u );
EDMA3_DRV_setOptField ( hEdma, chId[0], EDMA3_DRV_OPT_FIELD_ITCCHEN, 1u );
EDMA3_DRV_setOptField ( hEdma, chId[0], EDMA3_DRV_OPT_FIELD_TCCHEN, 1u );
myCbData[1].numTrs = 288;
myCbData[1].numTrCnt = 0;
EDMA3_DRV_setSrcParams ( hEdma, chId[1], (capYbuffer),
EDMA3_DRV_ADDR_MODE_INCR,
EDMA3_DRV_W8BIT );
EDMA3_DRV_setDestParams ( hEdma, chId[1], (storeCbbuffer1),
EDMA3_DRV_ADDR_MODE_INCR,
EDMA3_DRV_W8BIT );
EDMA3_DRV_setSrcIndex ( hEdma, chId[1], 4, 2880 );
EDMA3_DRV_setDestIndex ( hEdma, chId[1], 1, 392 );
EDMA3_DRV_setTransferParams ( hEdma, chId[1], 1, 360, 288, 360, EDMA3_DRV_SYNC_AB );
EDMA3_DRV_setOptField ( hEdma, chId[1], EDMA3_DRV_OPT_FIELD_TCINTEN, 1u );
EDMA3_DRV_setOptField ( hEdma, chId[1], EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u );
EDMA3_DRV_setOptField ( hEdma, chId[1], EDMA3_DRV_OPT_FIELD_ITCCHEN, 1u );
EDMA3_DRV_setOptField ( hEdma, chId[1],DMA3_DRV_OPT_FIELD_TCCHEN, 1u );
myCbData[2].numTrs = 288;
myCbData[2].numTrCnt = 0;
EDMA3_DRV_setSrcParams ( hEdma, chId[2], (capYbuffer + 2),
EDMA3_DRV_ADDR_MODE_INCR,
EDMA3_DRV_W8BIT );
EDMA3_DRV_setDestParams ( hEdma, chId[2], (storeCrbuffer1),
EDMA3_DRV_ADDR_MODE_INCR,
EDMA3_DRV_W8BIT );
EDMA3_DRV_setSrcIndex ( hEdma, chId[2], 4, 2880 );
EDMA3_DRV_setDestIndex ( hEdma, chId[2], 1, 392 );
EDMA3_DRV_setTransferParams ( hEdma, chId[2], 1, 360, 288, 360, EDMA3_DRV_SYNC_AB );
EDMA3_DRV_setOptField ( hEdma, chId[2], EDMA3_DRV_OPT_FIELD_TCINTEN, 1u );
EDMA3_DRV_setOptField ( hEdma, chId[2], EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u );
EDMA3_DRV_setOptField ( hEdma, chId[2], EDMA3_DRV_OPT_FIELD_ITCCHEN, 1u );
EDMA3_DRV_setOptField ( hEdma, chId[2], EDMA3_DRV_OPT_FIELD_TCCHEN, 1u );
EDMA3_DRV_enableTransfer ( hEdma, chId[0], EDMA3_DRV_TRIG_MODE_MANUAL );
EDMA3_DRV_enableTransfer ( hEdma, chId[1], EDMA3_DRV_TRIG_MODE_MANUAL );
EDMA3_DRV_enableTransfer ( hEdma, chId[2], EDMA3_DRV_TRIG_MODE_MANUAL );
