Question about HDVICP's BFSW usage

xiafeimao

Hi,all

The platform is DM6467T,we want to use EDMA to transfer encoded bitstream in STRBUF of HDVICP0.

So we first switch STRBUF to CPDMA by configuring BFSW register(bfsw_master0) ,then configure EDMA to work.

But when EDMA finishes,the result is that the data allocated in destination memory seems repeated in terms of 8 bytes like below:

"....

DE 8A F0 73 12 C1 5D 4F DE 8A F0 73 12 C1 5D 4F

.....

We check the data before switching STRBUF to DMA(then it's connect to ECD),it's all the same like the data patern above.

So we analyse that the BFSW maybe not work,when EDMA want to read data in STRBUF,it still connects to ECD.

Is there any reasons for this situation?

THANKS for HELP!

over 14 years ago

0 Kapil Ahuja over 14 years ago

TI__Intellectual 1970 points

Xiafeimao,

How did you check the data before switching the STRBUF to DMA? When the master of STRBUF is ECD, then the DSP/ARM968 cannot view the STRBUF memory.

To me it looks like the BFSW register is not programmed correctly, and ECD is still the master when you are trying to DMA the data.

Can you please check the BFSW settings again? If you still do not resolve the issue, please share the values that you are programming for the BFSW register (when connected to ECD, and then when you are switching it to DMA). We will take a look.

Regards,

Kapil

0 xiafeimao over 14 years ago in reply to Kapil Ahuja

Prodigy 40 points

Kapil:

Before the EDMA to transfer bitstream data from STRBUF, I have changed the value of BFSW_master0 register from 0xF to 0x0.

When the BFSW_master0 value is 0xF, I see the content under the location 0x0211C000 through the CCS_view memory windows.The value is "DE 8A F0 73 12 C1 5D 4F DE 8A F0 73 12 C1 5D 4F ... ",just the same as the result of EDMA.

I repeat run my project several times without change anything of the project, and several times the result of the EDMA is correct, and several timers the result of the EDMA is wrong .

It seems that after I changed the value of BFSW_master0 register, The master of STRBUF is not change immediately. So I want to know after the value of BFSW_master0 register has changed, how many cycles should I wait for to make sure the master of STRBUF have changed to DMA.

The following is the piece of code I used to configure BFSW and EDMA:

volatile unsigned int *bfswmaster0 = (unsigned int *)(0x02001110);

  *bfswmaster0 = 0;
  currDma->OPT = 0x0011B00C;
  currDma->SRC = 0x4041c000 + ecdRegs->DMAPTR;
  currDma->A_B_CNT = 0x00010800;
  currDma->DST = (U32)bsStartAddr;
  currDma->S_D_BIDX = 0x0;
  currDma->LINK_BCNTRLD = 0x0ffff;
  currDma->S_D_CIDX = 0x0;
  currDma->CCNT = 0x1;

  while(*bfswmaster0 != 0)
   ;

  REG(ESR) |= 0x08000000;
  while( (REG(IPR) & 0x08000000) != 0x08000000)
   ;
  REG(ICR) |= 0x08000000;

*bfswmaster0 = 0xf;

0 Kapil Ahuja over 14 years ago in reply to xiafeimao

TI__Intellectual 1970 points

Xiafeimao,

The change in mastership of the STRBUF will be immediate. The CPU cannot move ahead till the BFSW register is completely written into.

I think the problem is REG(ESR) |= 0x08000000 and REG(ICR) |= 0x08000000;

Replace it by REG(ESR) = 0x08000000 and REG(ICR) = 0x08000000. You do not have to OR these registers. Also you can safely remove the wait on the BFSW (while(*bfswmaster0 != 0)).

Please try this and let me know if it solves your problem.

Regards,

kapil

0 xiafeimao over 14 years ago in reply to Kapil Ahuja

Prodigy 40 points

Kapil,

I have tryed as you say, but the EDMA data still wrong as the same.

Any other suggestion?

Regards,

Xiafeimao

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Question about HDVICP's BFSW usage