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Do you share the detail functional block diagram of DPLL_PER on AM5728? I can find the functional block diagram of DPLL_HDMI at Figure 11-18; however, I cannot find the information of DPLL_PER.
Thank you for you reply.
However, I've already confirmed Figure 3-55, 3.6.3.3 and 3.6.3.4.
Could you share the internal block diagram of "Clock generator" for DPLL_PER?
