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66AK2L06: Deterministic Latency and Timing Between Multiple Devices and Discrete ADCs

Jhoneldrick Millares
Prodigy 140 points
Part Number: 66AK2L06

Hi E2E Community,

I'm currently interested in running two 66AK2L06s in parallel with 2 discrete ADCs on each device communicating via JESD. 

I have a few concerns about timing and synchronization first between the ADCs and second between the two DSP devices. 

Looking at the TIDEP0081 Wideband Receiver Design I see that the first problem can be addressed via the LMK04828 Jitter Cleaner that's available on the K2L-HSP FMC (DLC) Deterministic Latency Card. Is this card available for purchase?

As for the second problem, are there any suggestions for synchronization mechanisms (lockstep, etc) between two 66AK2L06 devices? 

Thank You!

  • 0
    TI__Mastermind 37500 points
    Hello,
    Please contact the third party provider Azcom Italy about the DLC card. It is used to adapt the CN16 connector on the EVM
    To a JESD Tx (from ADC) and to a JESD Rx (to DAC). If you map the signals to the existing JESD lane connections, you can either directly connect, or make an interposer as well

    Depending on the JESD-ADC selected, the JESD lane mapping also needs to be reviewed. There are one, two, four lane mappings.
    The order of the I or IQ samples, needs to be reviewed also. Typically for “F” parameter we have 2 for parallel IQ or I, and we have 4 for interleaved IQ. “LMFSHD” are described in the DFE User Guide, with specific serdes rates, and IQ rates in DFE.
    DFE then provides signal processing from the IQN Baseband IQ rate to the Data converter stream rate, before JESD204B conversion.

    To share between two EVMs and two ADCs, you would need to provide a common 122.88Mhz clock, JESD clock. There are two synchronization methods that can be used, you can combine the SYNC signal between two platforms, and add wait loops in the software for both platforms to synchronize at the JESD input side. Typically for an ADC which is transmitting, the K2L06 would send SYNCOUT, this would be received by the ADC as SYNCIN. You would logically AND the two SYNCOUTs and buffer them to the two SYNCINs (LVDS) You would need to look in the JESD204 specification for this.

    The IQN interface has an external sync capability which is used for synchronizing a 5ms-10ms frame from an external timing signal.
    There are also timing and sync signals to the DSP, DMA transfer, and DFE block to synchronize from the IQN timers. Look for the term “EXTERNAL SYNC”.

    Regards,
    Joe Quintal