AM3354: LCDC pixel clock issue

shigehiro tsuda

Part Number: AM3354

Hi,

The following LCDC waveforms are output.
The PCLK clock stops at the falling edge of VSYNC.
In the case of active mode, I think that PCLK does not stop, but is there any register setting where PCLK is stopped?

Best Regards,
Shigehiro Tsuda

over 7 years ago

0 Biser Gatchev-XID over 7 years ago

TI__Guru**** 393215 points

Hi,

Pixel clock is held in inactive state for passive displays.

0 shigehiro tsuda over 7 years ago in reply to Biser Gatchev-XID

Mastermind 9490 points

Hi Biser,

Thank you for quick reply.
Is PCLK stopped when used in active display mode instead of passive display mode?
After confirming the register, active display mode (cfg_lcdtft = '1') is set.

Best Regards,
Shigehiro Tsuda

0 Biser Gatchev-XID over 7 years ago in reply to shigehiro tsuda

TI__Guru**** 393215 points

Pixel clock should be continuous in raster active mode.

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AM3354: LCDC pixel clock issue