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Linux/AM5726: DDR3 configuration question

Janice Nygren
Intellectual 760 points

Part Number: AM5726

Tool/software: Linux

Hi,

I'm using the EMIF tool http://www.ti.com/lit/an/sprac36b/sprac36b.pdf to understand how to config DDR3. It seems some register options are not shown in the spread sheet, for example, EBANK_POS field is always set to 0 in the generated u-boot code, is that right? But the SDK 4.3.0.5 source code has it set to 1.

The TRM says ROWSIZE in EMIF_SDRAM_CONFIG is not used only if EBANK_POS=0 and IBANK_POS=0. Out of curiosity, I set ROWSIZE to a wrong size, while keeping EBANK_POS=1 as is.

SDK source setting: 4c000008: 61851b32 08000000

My test setting1: 4c000008: 61851bb2 08000000

My test setting2: 4c000008: 61851ab2 08000000       

Surprisingly the device still works with my test settings. Why doesn't the wrong row size affect the functionality here?

Thank you!

Jan

  • 0
    TI__Guru**** 393215 points
    The DDR experts have been notified. They will respond here.
  • 0 in reply to Biser Gatchev-XID
    TI__Genius 9655 points

    Please see the snapshot from the AM5726 TRM Page: 3409. The ROWSIZE field is not used when the IBANK_POS and EBANK_POS are set to 0. Please let us know if you have any other follow-up questions.

    Regards, Siva

  • 0 in reply to sivak
    Intellectual 760 points

    Hi Siva,

    In my test cases, EBANK_POS =1, i.e.  0x4C0000C is set to 0x08000000, so this case row size should have been used. Please see my captured settings.

    >> My test setting1: 4c000008: 61851bb2 08000000

    >> My test setting2: 4c000008: 61851ab2 08000000 

    Thanks,

    Jan

  • 0 in reply to Janice Nygren
    TI__Genius 9655 points
    Jan

    With the incorrect row size setting, are you able to access the entire memory region?

    Regards, Siva
  • 0 in reply to sivak
    TI__Genius 9655 points
    Jan

    Please provide an update on this issue. We are unable to comment on wrong settings and impact on the behavior without more information.


    Regards, Siva
  • 0 in reply to sivak
    Intellectual 760 points
    Hi Siva, for my experiment on EVM, in u-boot I changed EMIF_SDRAM_CONFIG @4c000008 to 0x61851bb2, left EMIF_SDRAM_CONFIG _2 as is 0x08000000. I was able to boot up the kernel and file system just fine. I don't know if this covers the whole memory range. See my u-boot commands:
    => md 0x4c000008
    4c000008: 61851b32 08000000 00001035 00001035 2..a....5...5...
    4c000018: cccf36ab cccf36ab 308f7fda 308f7fda .6...6.....0...0
    4c000028: 409f88a8 409f88a8 11220c0c 11220c0c ...@...@.."...".
    4c000038: 0000f2f0 0000f0f0 00000000 00000000 ................
    4c000048: 00000000 00000000 00000000 0a500000 ..............P.
    4c000058: 9000190a 00042727 00002011 00000000 ....''... ......
    4c000068: 00000000 00000000 00000000 00000000 ................
    4c000078: 00000000 00000000 000c452e 0000f112 .........E......
    4c000088: 00010000 00000000 c2be19c6 00000000 ................
    4c000098: 00050000 00050000 00000000 00000000 ................
    4c0000a8: 00000000 00000000 00000000 00000000 ................
    4c0000b8: 00000000 00000000 00000000 00000000 ................
    4c0000c8: 5007190b 00000000 00000000 00000000 ...P............
    4c0000d8: 00000000 00000000 00000000 0e24400b .............@$.
    4c0000e8: 0e24400b 00000000 00000000 00000000 .@$.............
    4c0000f8: 00000000 00000000 00000000 00000000 ................
    => mw 0x4c000008 0x61851bb2
    => md 0x4c000008
    4c000008: 61851bb2 08000000 00001035 00001035 ...a....5...5...
    4c000018: cccf36ab cccf36ab 308f7fda 308f7fda .6...6.....0...0
    4c000028: 409f88a8 409f88a8 11220c0c 11220c0c ...@...@.."...".
    4c000038: 0000f2f0 0000f0f0 00000000 00000000 ................
    4c000048: 00000000 00000000 00000000 0a500000 ..............P.
    4c000058: 9000190a 00042727 00002011 00000000 ....''... ......
    4c000068: 00000000 00000000 00000000 00000000 ................
    4c000078: 00000000 00000000 000c4535 0000f118 ........5E......
    4c000088: 00010000 00000000 6142f696 00000000 ..........Ba....
    4c000098: 00050000 00050000 00000000 00000000 ................
    4c0000a8: 00000000 00000000 00000000 00000000 ................
    4c0000b8: 00000000 00000000 00000000 00000000 ................
    4c0000c8: 5007190b 00000000 00000000 00000000 ...P............
    4c0000d8: 00000000 00000000 00000000 0e24400b .............@$.
    4c0000e8: 0e24400b 00000000 00000000 00000000 .@$.............
    4c0000f8: 00000000 00000000 00000000 00000000 ................
    => boot
  • 0 in reply to Janice Nygren
    TI__Genius 9655 points
    Jan

    With the settings you shared, the row size is being either set to either 15 bits or 16 bits. I'm not sure about the row size of the DDR memory you are using. Basically, the impact of this setting will be that you will not be able to access the full memory address range. This should not impact your functionality. At this point, I'm not sure if we can comment any further. Let me know if you have any other open questions.

    Regards, Siva