Hi,
I'm trying to interface to an altera fgpa throuh vlynq with DM6467 as master and TES altera VLYNQ IP.
When I insmod saVlynq.ko, I get
Starting Vlynq Test Case...
VLYNQ MASTER:Success in Initializing vlynq configuration
VLYNQ ID from config_bridge = 0
Link not detected 1
VLYNQ MASTER: Failed to initialize the vlynq 0xc8430000
VLYNQ MASTER:The error msg: Error in configuring clocks.
VLYNQ MASTER:Error in LOCAL & PEER vlynq configuration.
VLYNQ Initialization Failed.
when the FPGA IP is not correctly connected.
Otherwise, my kernel hangs with no error message. In that case, Bit 0 in the VLYNQ status register (LINK bit) is set to 1.
What can cause the system to hang when I try to initialize the link with the FPGA.
Thanks
Yann