Linux: Ethernet issue on custom board

Nevena Stojanovic

Other Parts Discussed in Thread: DP83867IR

Tool/software: Linux

Hi,

We have custom board based on Tda2Px Eve board. RGMII1 interface use PHY DP83867IR . The PHY address is correct. I found that the value in CTRL_CORE_PAD_VIN2A_D23 was set to the wrong value.

It can recognize the address but the link is not detected.

This is part of device-tree file:

&cpsw_emac0 {
   phy_id = <&davinci_mdio>, <2>;
   phy-mode = "rgmii-id";
   dual_emac_res_vlan = <1>;
};

&cpsw_emac1 {
   phy_id = <&davinci_mdio>, <0>;
   phy-mode = "rgmii-id";
   dual_emac_res_vlan = <2>;
};

&davinci_mdio {
   dp83867_0: ethernet-phy@2 {
       reg = <2>;
       ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
       ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
       ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
       ti,min-output-impedance;
       ti,dp83867-rxctrl-strap-quirk;
   };

   dp83867_1: ethernet-phy@0 {
       reg = <0>;
       ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
       ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
       ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
       ti,min-output-impedance;
       ti,dp83867-rxctrl-strap-quirk;
   };
};

ethtool eth1 shows:

Settings for eth1:

Supported ports: [ TP MII ]

Supported link modes: 10baseT/Half 10baseT/Full

100baseT/Half 100baseT/Full

1000baseT/Half 1000baseT/Full

Supported pause frame use: No

Supports auto-negotiation: Yes

Advertised link modes: 10baseT/Half 10baseT/Full

100baseT/Half 100baseT/Full

1000baseT/Half 1000baseT/Full

Advertised pause frame use: No

Advertised auto-negotiation: Yes

Speed: 10Mb/s

Duplex: Half

Port: MII

PHYAD: 0

Transceiver: external

Auto-negotiation: on

Supports Wake-on: d

Wake-on: d

Current message level: 0x00000000 (0)

Link detected: no

dmesg | grep eth :

[ 1.975495] cpsw 48484000.ethernet: Detected MACID = f4:84:4c:10:63:ac

[ 1.982143] cpsw 48484000.ethernet: cpts: overflow check period 800

[ 1.989136] cpsw 48484000.ethernet: cpsw: Detected MACID = f4:84:4c:10:63:ad

[ 12.049585] net eth1: initializing cpsw version 1.15 (0)

[ 12.077369] net eth0: initialized cpsw ale version 1.4

[ 12.099079] net eth0: ALE Table size 1024

[ 12.299595] net eth1: phy found : id is : 0x2000a231

[ 12.353035] IPv6: ADDRCONF(NETDEV_UP): eth1: link is not ready

[ 12.384578] net eth0: initializing cpsw version 1.15 (0)

[ 12.434998] net eth0: phy "48485000.mdio:02" not found on slave 0, err -19

[ 12.469853] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready

[ 1.953208] davinci_mdio 48485000.mdio: davinci mdio revision 1.6

[ 1.966517] davinci_mdio 48485000.mdio: phy[0]: device 48485000.mdio:00, driver TI DP83867

[ 2.228746] davinci-mcasp 48464000.mcasp: DAI is shared

[ 2.234852] davinci-mcasp 48474000.mcasp: DAI is shared

Could you please provide me any reference to solve this issue?

Regards, Nevena

over 7 years ago

0 Srirama Govindarajan over 7 years ago

TI__Expert 8250 points

Hi
When you are using uboot the pin mux is configured from bootloader - please review the pin mux configuration accordingly.
Are there any other changes on the Custom board aside of a direct replacement of the PHY, have reviewed the hookup in comparison with the TI EVM

0 Nevena Stojanovic over 7 years ago in reply to Srirama Govindarajan

Intellectual 540 points

Hi,

could you please take a look at our rgmii shematic. According to this shemtic PHY address is 0x0. I checked out registers from user-space and seems that all values are correct. Do you have ideas what can cause the issue Link detected: no ?

Regards,

Nevena

0 Stanislav Stilyanov over 7 years ago in reply to Nevena Stojanovic

TI__Mastermind 24990 points

Hi Nevena,

Sorry for some stupid questions, but it wasn't clear to me:

- Do you have some network device connected? Ethernet Switch or PC?

- Do you see 'link LED' to light up? Activity LED?

- Does this PHY has an ability to change MDIO address? I didn't see any pins and I wasn't able to download the datasheet yet.

- Do MDIO CLK and DATA have pullups?

Regards,

Stan

0 Stanislav Stilyanov over 7 years ago in reply to Stanislav Stilyanov

TI__Mastermind 24990 points

Looks like address is strapped on pins RX_D0, RX_D2, RX_D4 in a 4-level manner. RX_D4 is open therefore already latches 0. Remains to check that RX_D0, RX_D2 are not driven (or pulled down) by SoC, long enough, so they latch zeroes as well.

Also, there was a command line MDIO utility which can scan all 32 addresses, I don't remember details unfortunately.

0 Nevena Stojanovic over 7 years ago in reply to Stanislav Stilyanov

Intellectual 540 points

Hi,

-Yes, it's connected through ethernet switch but the LED link has no activity.

-MDIO CLK and DATA are directly connected to SOC and according to data sheet:

BALL | BALL NAME | BALL_RESET_STATE | PULL UP/DOWN TYPE

MDIO CLK : D3 | vin2a_d10 | PD | PU/PD

DATA: F4 | vin2a_d11 | PD | PU/PD

RX_D0: A4 | vin2a_d23 | PD | PU/PD

RX_D2: B4 | vin2a_d21 | PD | PU/PD

mdio list gives this output:

ethernet@48484000:

0 - TI DP83867 <--> ethernet@48484000

Regards,

Nevena

0 Nevena Stojanovic over 7 years ago in reply to Nevena Stojanovic

Intellectual 540 points

Hi,

just to add this to previous comment.

In data-sheet I found that RX_DV/RX_CTRL requires to be strapped:

In our case RX_DV/RX_CTRL are not strapped and we got MODE 1 .

When I type ethtool eth1 I got : auto-negotiation: Yes.

Can you clarify this?

Regards,

Nevena

0 Stanislav Stilyanov over 7 years ago in reply to Nevena Stojanovic

TI__Mastermind 24990 points

Hi Nevena,
Looks like PHY takes address 0x0 and no issue with it.
- Then, can you please read registers at addresses 0x0 and 0x1, a or do a complete PHY register dump?
- Can you tell the product ID of the RJ45 connector?

Thanks,
Stan

0 Stanislav Stilyanov over 7 years ago in reply to Nevena Stojanovic

TI__Mastermind 24990 points

That was my next comment. This pin needs strap pins explicitly, since mode 1 [00] is reserved . This looks like mandatory requirement, but I can't confirm, since I'm not expert of this PHY.
More globally, I would recommend to re-visit all settings that strap pins latch are meeting your requirements. Most of them can be re-set later by registers, so this task becomes somewhat more complex.

0 Nevena Stojanovic over 7 years ago in reply to Stanislav Stilyanov

Intellectual 540 points

Hi,

with mdio read dev addr I got:

=> mdio read ethernet@48484000 0x0