AM5K2E02: Clocking options for AM5K2E0x

Hi Carlos,

Regarding requirements always follow the ones listed in the Datasheet, because it is the most up to date document. Also the other documents, like the hardware design guide is a common document for all keystone II devices (K2H, K2E, etc..).

Having that said, you can also refer to the Clocking Spreadsheet (www.ti.com/.../sprac72.pdf ) and the Clocking Design Guide (www.ti.com/.../sprabi4.pdf ).

As for recommending a device with temperature range of 105 degrees or above, have a look at the devices that TI provides:
www.ti.com/.../products.html

You can see there are some with temp range of up to 125 degrees. Note that you have to keep in mind the datasheet requirements.

Best Regards,
Yordan

Carlos,

The differential clock requirements into the core PLLs (including the NETCP PLL) are not difficult to meet.  Any quality differential LVDS clock driver can meet these requirements.  The difficult requirements are those for the SERDES reference clocks (like PCIe or SGMII).  They have very strict jitter requirements that require clock sources with very low phase jitter.  As recommended by Yordan, clock generators from the CDCE, CDCM and CDCI series are required for the SERDES reference clocks.

Tom

Carlos,

If you want specific recommendations, the CDCM6208 used on the EVM is a recommended solution.  We are using the CDCI6214 on newer EVMs which is also equally applicable.

Tom

Carlos,

Looking at the selection guide linked above, it appears that the only 105C option for the SERDES reference clocks is the CDC421AXXX family of devices.  They do not have the programmability but they have the specs and output the required frequencies.

Tom