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AM3352: Performance degradation with cache disabled

Ilya Kogan77
Intellectual 355 points

Part Number: AM3352
Other Parts Discussed in Thread: AM3359, AM5706

I got coremark numbers on a couple of hardware platforms. What could be a reason for such a performance degradation? 

Coremark 1.0 results
Olimex AM3352 EVB (400MHz DDR3, CL=6, CWL=5), enabled branch prediction Cache enabled Cache disabled L2 Cache enabled L2 and I-cache enabled L2 and  D-cache enabled I-cache and D-cache enabled
MPU clock 1000MHz 1112.846941 23.706515 23.70728 59.871808 344.347633 1112.943728
MPU clock 800MHz 890.382027 22.552103 22.560954 56.703329 275.480536 891.006599
MPU clock 600MHz 667.815758 20.792467 20.801641 52.082539 206.611331 668.335052

 AM3352 (303MHz DDR3, CL=5, CWL=5), enabled branch prediction
MPU clock 500MHz 556.49442 17.032291 46.10939 177.524694

Because of product safety requirements cache may have to be disabled to avoid the necessity of testing it periodically.  

  • 0
    TI__Guru**** 393215 points
    The factory team have been notified. They will respond here.
  • 0 in reply to Biser Gatchev-XID
    TI__Guru* 95821 points
    I'm not familiar with this benchmark. Can you give details on where specifically you are seeing poor performance?

    James
  • 0 in reply to JJD
    Intellectual 355 points

    CoreMark is a synthetic benchmark that measures the performance of central processing units (CPU) used in embedded systems. It was developed in 2009 by Shay Gal-On at EEMBC.

     The code is written in C and contains implementations of the following algorithms: list processing (find and sort), matrix manipulation (common matrix operations), state machine (determine if an input stream contains valid numbers), and CRC.

    Coremark source code a available for free download, and can be ported to any compiler/microprocessor.

    The result is a single number that is indicative of overall CPU performance. These are the numbers in the table I posted.

    The same code is executed for different cache configurations.

    https://en.wikipedia.org/wiki/Coremark

    https://www.eembc.org/coremark//index.php

    I tried inserting a coremark readme file but it did not work.  

  • 0 in reply to JJD
    Intellectual 355 points
    CoreMark is a synthetic benchmark that measures the performance of central processing units (CPU) used in embedded systems. It was developed in 2009 by Shay Gal-On at EEMBC.
     The code is written in C and contains implementations of the following algorithms: list processing (find and sort), matrix manipulation (common matrix operations), state machine (determine if an input stream contains valid numbers), and CRC.
    Coremark source code a available for free download, and can be ported to any compiler/microprocessor.
    The result is a single number that is indicative of overall CPU performance. These are the numbers in the table I posted.
    The same code is executed for different cache configurations.
    en.wikipedia.org/.../Coremark
    www.eembc.org/.../index.php
    I tried inserting a coremark readme file but it did not work.
  • 0 in reply to Ilya Kogan77
    TI__Guru* 95821 points

    There will be obvious performance degradation with the cache disabled.  Can you explain what you were expecting versus what results you got?  

    Regards,

    James

  • 0 in reply to JJD
    TI__Guru 50170 points
    Hi, Ilya,

    The performance looks as expected. When cache is disabled in a processor, 10-100 times performance degradation is expected. Higher the processor speed compared to memory the greater the degradation is also expected. Similarly the higher end the processor is the greater the degradation. For A8 processor, there will be stalls for each action when reading the instruction from memory, accessing data (read and write), etc. That is easily 50-300 stalls per instruction executed, or ~99% stalls.

    If safety is a concern, would TI Hercules MCU with a Cortex R core, www.ti.com/.../overview.html, be the alternative to achieve better performance?

    Rex
  • 0 in reply to Rex Chang
    Intellectual 355 points

    Thank you for the explanation. We did consider Hercules MCUs but MPU clock frequency/EMAC limitations makes it problematic.

    Ilya

  • 0 in reply to Ilya Kogan77
    TI__Guru 50170 points
    Hi, Ilya,

    Thanks for the info. If you don't have any more questions, I'll close this thread. I appreciate if you click "Resolved" button. Thanks!

    Rex
  • 0 in reply to Ilya Kogan77
    TI__Guru* 86115 points
    Hi Ilya
    I see that we have clarified that the degradation that you see is somewhat in expected range and you have verified the response.
    I also see that you are trying to look for processors for safety application and Hercules is not meeting your requirements

    Is there anything we can further help you with to help on the processor evaluation/selection?

    Do you have more inputs on James's query "Can you explain what you were expecting versus what results you got? "
    - I am not sure if cache disabling is the right approach in general for this class of processors , additionally we will have roadmap processors with fault injection support on memories (will not be able to share much details on that on public forum) - so understanding why you did these experiments and what concerns it generates based on results - will be helpful


    Any further elaboration on EMAC limitation on Hercules - I am assuming your comment on MPU clock frequency is simply that it does not meet your performance requirements?
  • 0 in reply to Mukul Bhatnagar
    Intellectual 355 points

    Hi Mukul,

    Yes, Hercules is too slow, and EMAC (if there is one) is 10/100Mbps only.

    A safety critical device must have all it's components tested periodically. This includes instruction and data caches.

    Cache testing may require a lot of MPU bandwidth (can you provide any suggestions?) so an idea was to disable caches

    to see if the MPU performance degradation will not be significant. It was significant. Other options would be using 2 MPUs processing the same data

    (introduces a lot of design complexity), or multiple cores.

    AM3352 is a good candidate as it supports MPU clock up to 1000MHz, and there is an option of using AM3359 if Industrial 

    Ethernet if it becomes a requirement in the future.

    AM5706 may be another possibility but $21+ vs $6 is hard to justify (and $600 for an evaluation board seems like like a significant investment

    with future unknown).

    Thanks,

    Ilya

  • 0 in reply to Ilya Kogan77
    TI__Guru* 86115 points

    Hi Ilya
    Thanks for the additional background. I confered with folks with more knowledge on safety then I do, here are some points to consider
    In general safety certification is a signficant investment - so I am hoping EVM tool cost is not that big of a deterrent?
    If it is, you can also consider the community board for AM572x family http://beagleboard.org/x15

    Can you share what safety certification you are targetting for this application , what standard and what level?
    Please do keep in mind that unlike our Hercules portfolio, AM335x or AM57x was not designed for safety certification, so in general there is additional onus on the customer for safety certification
    as the only collateral we have is what you see on the product folders.

    In general, if the processor is designed for safety diagnostics (like Hercules) testing caches is part of the capability. Tradeoffs have to be considered on testing the cache incrementally
    vs entire cache at once to manage the performance hit.

    For AM335x/AM57x you will likely need to use some indirect approach aand align with auditors if they accept the approach.

    Specifically for your question on testing - we have seen some customers leverage CP15 commands to test the caches (details in Cortex A8 TRM r3p2 from arm.com section 3.2)

    Hope this helps some.

    Regards
    Mukul