Hi All,
I need 1280 x 720 @ 60Hz display configuration with OMAP3503 and need 74.25MHz display pixel clock for this. As per OMAP datasheet, it supports this configuration at 74.25MHz Pixel Clock. I am using 12MHz system clock for OMAP.
Now, to configure Display PCLK as 74.25MHz, DPLL4 should output a frequency that is multiple of 74.25 i.e. 297, 594, 861, 1188 and so on. This is feasible and can be done easily by changing the DPLL4, multiplier and divider values.
But DPLL4 is also the source for other peripheral clocks. Especially, 96MHz functional clock is generated from DPLL4 which is used by SD/MMC, UART and I2C interfaces.
For getting this 96MHz clock as well as 74.25MHz display PCLK, the min DPLL4 output should be 9504MHz. But the value of divisor for getting 96MHz from DPLL4 output can be Max 16 only as per OMAP datasheet (as per the DIV_96M bit field in the register CM_CLKSEL3_PLL[4:0] ). Therefore, the max O/P of DPLL4 should not exceed 96 x 16 = 1536MHz.
So, it seems that with 74.25MHz display PCLK, the 96MHz peripheral clock cannot be generated exactly and the idea of using some clock rate other than 96MHz is a bit confusing to me as the 96MHz is described as a fixed clock in OMAP datasheet. I feel there should be some workaround for this.
Has anyone tried configuring display PCLK as 74.25MHz? If yes, what is the clock rate used for 96MHz peripheral functional clock because if this clock is changed, I need to change a lot of other clocks for SD/MMC, UART, I2C etc.
Vini
