In video display port raw data display mode, the display port should be sync to external controlled HSYNC, VSYNC and FVID signals. In my application, I used an FPGA connected with DSP video port. The FPGA will provide the HSYNC, VSYNC and FVID signals to DSP video port. However I checked the video port signals using an oscilloscope, I found that the HSYNC/VSYNC/FVID could not affect the video port timing, the video port will output pixel data just according to the timing restricted in the video display related registers.
In order to check this problem, I fixed the HSYNC = 0 and VSYNC = 0, the video port outputs pixel data according to video display timing registers; even if I fixed the HSYNC = 1 and VSYNC = 1, the video port still outputs pixel data accordingly.
It seems that the external sync signals could not control the pace of the output pixel data. The following is my display port configuration parameter definition in PSP driver style:
#define HDIM_DIS_RAW_16BIT { \
VPORT_MODE_RAW_16BIT, /* dmode:3 */ \
VPORT_FLDOP_PROGRESSIVE, /* fldOp:3 */ \
\
VPORT_SCALING_DISABLE, /* scale:1 */ \
VPORT_RESMPL_DISABLE, /* resmpl:1 */ \
VPORTDIS_DEFVAL_ENABLE, /* defValEn:1 */ \
VPORTDIS_BPK_10BIT_NORMAL, /* bpk10Bit:1 */ \
\
VPORTDIS_VCTL1_HSYNC, /* vctl1Config */ \
VPORTDIS_VCTL2_VSYNC, /* vctl2Config */ \
VPORTDIS_VCTL3_FLD, /* vctl3Config */ \
7, /* extCtl:3 */ \
\
HDIM_DIS_RAW_16BIT_LINE_SZ+30, /* frmHSize */ \
HDIM_DIS_RAW_16BIT_NUM_LINES+5, /* frmVSize */ \
\
0, /* imgHOffsetFld1 */ \
0, /* imgVOffsetFld1 */ \
HDIM_DIS_RAW_16BIT_LINE_SZ, /* imgHSizeFld1 */ \
HDIM_DIS_RAW_16BIT_NUM_LINES, /* imgVSizeFld1 */ \
\
0, /* imgHOffsetFld2 */ \
0, /* imgVOffsetFld2 */ \
0, /* imgHSizeFld2 */ \
0, /* imgVSizeFld2 */ \
\
HDIM_DIS_RAW_16BIT_LINE_SZ, /* hBlnkStart */ \
0, /* hBlnkStop */ \
\
0, /* vBlnkXStartFld1 */ \
1, /* vBlnkYStartFld1 */ \
0, /* vBlnkXStopFld1 */ \
3, /* vBlnkYStopFld1 */ \
\
0, /* vBlnkXStartFld2 */ \
0, /* vBlnkYStartFld2 */ \
0, /* vBlnkXStopFld2 */ \
0, /* vBlnkYStopFld2 */ \
\
0, /* xStartFld1 */ \
1, /* yStartFld1 */ \
\
0, /* xStartFld2 */ \
0, /* yStartFld2 */ \
\
HDIM_DIS_RAW_16BIT_LINE_SZ+9, /* hSyncStart */ \
HDIM_DIS_RAW_16BIT_LINE_SZ+19, /* hSyncStop */ \
\
HDIM_DIS_RAW_16BIT_LINE_SZ, /* vSyncXStartFld1 */ \
1, /* vSyncYStartFld1 */ \
HDIM_DIS_RAW_16BIT_LINE_SZ+14, /* vSyncXStopFld1 */ \
2, /* vSyncYStopFld1 */ \
\
0, /* vSyncXStartFld2 */ \
0, /* vSyncYStartFld2 */ \
0, /* vSyncXStopFld2 */ \
0, /* vSyncYStopFld2 */ \
\
0, /* yClipLow, unused */ \
0, /* yClipHigh, unused*/ \
0, /* cClipLow, unused */ \
0, /* cClipHigh, unused*/ \
\
0x00, /* Default Y value */ \
0x00, /* Default Cb value */ \
0x00, /* Default Cr value */ \
\
VPORTDIS_RGBX_DISABLE, /* RGB extract disable */ \
1, /* incPix, for raw mode only */ \
\
(HDIM_DIS_RAW_16BIT_LINE_SZ >> 3), /* thrld */ \
\
3, /* numFrmBufs */ \
128, /* alignment */ \
VPORT_FLDS_MERGED, /* mergeFlds */ \
\
NULL, /* segId */ \
NULL /* hEdma */ \
}
